C8051F340 Datasheet, PDF (257/282 Pages) List of Unclassifed Manufacturers – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7
21.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, USB Start-of-Frame (SOF) capture
mode, or Low-Frequency Oscillator (LFO) Rising Edge capture mode. The Timer 3 operation mode is
defined by the T3SPLIT (TMR3CN.3), T3CE (TMR3CN.4) bits, and T3CSS (TMR3CN.1) bits.
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 3 (and/or the PCA) is clocked by an external preci-
sion oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
21.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is ‘0’ and T3CE = ‘0’, Timer 3 operates as a 16-bit timer with auto-reload.
Timer 3 can be clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided
by 8. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the
Timer 3 reload registers (TMR3RLH and TM3RLL) is loaded into the Timer 3 register as shown in
Figure 21.4, and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled,
an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled and
the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L) over-
flow from 0xFF to 0x00.
T3XCLK
SYSCLK / 12
0
External Clock / 8
1
SYSCLK
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
0
TR3
1
To ADC
TCLK
TMR3L TMR3H
TMR3RLL TMR3RLH
Reload
TF3H
TF3L
TF3LEN
T3CE
T3SPLIT
TR3
T3CSS
T3XCLK
Figure 21.8. Timer 3 16-Bit Mode Block Diagram
Interrupt
Rev. 0.5
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