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C8051F340 Datasheet, PDF (188/282 Pages) List of Unclassifed Manufacturers – Full Speed USB Flash MCU Family | |||
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C8051F340/1/2/3/4/5/6/7
A Bulk or Interrupt pipe can be shut down (or Halted) by writing â1â to the SDSTL bit (EOUTCSRL.5). While
SDSTL = â1â, hardware will respond to all OUT requests with a STALL condition. Each time hardware gen-
erates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to â1â. The
STSTL bit must be reset to â0â by firmware.
Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO. Note that if double buff-
ering is enabled for the target endpoint, it is possible for two packets to be ready in the OUT FIFO at a time.
In this case, hardware will set OPRDY to â1â immediately after firmware unloads the first packet and resets
OPRDY to â0â. A second interrupt will be generated in this case.
16.13.2.Endpoints1-3 OUT Isochronous Mode
When the ISO bit (EOUTCSRH.6) is set to â1â, the target endpoint operates in Isochronous (ISO) mode.
Once an endpoint has been configured for ISO OUT mode, the host will send exactly one data per USB
frame; the location of the data packet within each frame may vary, however. Because of this, it is recom-
mended that double buffering be enabled for ISO OUT endpoints.
Each time a data packet is received, hardware will load the received data packet into the endpoint FIFO,
set the OPRDY bit (EOUTCSRL.0) to â1â, and generate an interrupt (if enabled). Firmware would typically
use this interrupt to unload the data packet from the endpoint FIFO and reset the OPRDY bit to â0â.
If a data packet is received when there is no room in the endpoint FIFO, an interrupt will be generated and
the OVRUN bit (EOUTCSRL.2) set to â1â. If USB0 receives an ISO data packet with a CRC error, the data
packet will be loaded into the endpoint FIFO, OPRDY will be set to â1â, an interrupt (if enabled) will be gen-
erated, and the DATAERR bit (EOUTCSRL.3) will be set to â1â. Software should check the DATAERR bit
each time a data packet is unloaded from an ISO OUT endpoint FIFO.
188
Rev. 0.5
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