C8051F340 Datasheet, PDF (241/282 Pages) List of Unclassifed Manufacturers – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7
Table 20.1. SPI Slave Timing Parameters
Parameter
T_MCKH
T_MCKL
T_MIS
T_MIH
T_SE
T_SD
T_SEZ
T_SDZ
T_CKH
T_CKL
T_SIS
T_SIH
T_SOH
T_SLH
Description
Min
Max
Units
Master Mode Timing* (See Figure 20.8 and Figure 20.9)
SCK High Time
1 x T_SYSCLK
ns
SCK Low Time
MISO Valid to SCK Shift Edge
1 x T_SYSCLK
ns
1 x T_SYSCLK + 20
ns
SCK Shift Edge to MISO Change
0
ns
Slave Mode Timing* (See Figure 20.10 and Figure 20.11)
NSS Falling to First SCK Edge
2 x T_SYSCLK
ns
Last SCK Edge to NSS Rising
2 x T_SYSCLK
ns
NSS Falling to MISO Valid
4 x T_SYSCLK ns
NSS Rising to MISO High-Z
SCK High Time
5 x T_SYSCLK
4 x T_SYSCLK ns
ns
SCK Low Time
5 x T_SYSCLK
ns
MOSI Valid to SCK Sample Edge
2 x T_SYSCLK
ns
SCK Sample Edge to MOSI Change
2 x T_SYSCLK
ns
SCK Shift Edge to MISO Change
4 x T_SYSCLK ns
Last SCK Edge to MISO Change (CKPHA = 1
ONLY)
6 x T_SYSCLK 8 x T_SYSCLK ns
*Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
Rev. 0.5
241