LM3S2965_0711 Datasheet, PDF (81/574 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2965 Microcontroller
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows
RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible
to previous parts. The fields within the RCC2 register occupy the same bit positions as they do
within the RCC register as LSB-justified.
The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system
clock frequency for improved Deep Sleep power consumption.
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2800
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
USERCC2
reserved
SYSDIV2
reserved
Type R/W
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PWRDN2 reserved BYPASS2
reserved
OSCSRC2
reserved
Type RO
RO
R/W
RO
R/W
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
RO
RO
Reset
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31
30:29
28:23
22:14
13
12
11
Name
USERCC2
reserved
SYSDIV2
reserved
PWRDN2
reserved
BYPASS2
Type
R/W
RO
R/W
RO
R/W
RO
R/W
Reset
0
0x0
0x0F
0x0
1
0
1
Description
Use RCC2
When set, overrides the RCC register fields.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divisor
Specifies which divisor is used to generate the system clock from the
PLL output.
The PLL VCO frequency is 400 MHz.
This field is wider than the RCC register SYSDIV field in order to provide
additional divisor values. This permits the system clock to be run at
much lower frequencies during Deep Sleep mode. For example, where
the RCC register SYSDIV encoding of 1111 provides /16, the RCC2
register SYSDIV2 encoding of 111111 provides /64.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power-Down PLL
When set, powers down the PLL.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Bypass PLL
When set, bypasses the PLL for the clock source.
November 30, 2007
81
Preliminary