LM3S2965_0711 Datasheet, PDF (44/574 Pages) List of Unclassifed Manufacturers – Microcontroller

Memory Map
3 Memory Map
The memory map for the LM3S2965 controller is provided in Table 3-1 on page 44.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important: In Table 3-1 on page 44, addresses not listed are reserved.
Table 3-1. Memory Map^a
Start
End
Memory
0x0000.0000
0x2000.0000
0x2010.0000
0x2200.0000
0x2400.0000
FiRM Peripherals
0x4000.0000
0x4000.4000
0x4000.5000
0x4000.6000
0x4000.7000
0x4000.8000
0x4000.9000
0x4000.C000
0x4000.D000
0x4000.E000
Peripherals
0x4002.0000
0x4002.0800
0x4002.1000
0x4002.1800
0x4002.4000
0x4002.5000
0x4002.6000
0x4002.7000
0x4002.8000
0x4002.C000
0x4002.D000
0x4003.0000
0x4003.1000
0x0003.FFFF
0x2000.FFFF
0x21FF.FFFF
0x23FF.FFFF
0x3FFF.FFFF
0x4000.0FFF
0x4000.4FFF
0x4000.5FFF
0x4000.6FFF
0x4000.7FFF
0x4000.8FFF
0x4000.9FFF
0x4000.CFFF
0x4000.DFFF
0x4000.EFFF
0x4002.07FF
0x4002.0FFF
0x4002.17FF
0x4002.1FFF
0x4002.4FFF
0x4002.5FFF
0x4002.6FFF
0x4002.7FFF
0x4002.8FFF
0x4002.CFFF
0x4002.DFFF
0x4003.0FFF
0x4003.1FFF
Description
On-chip flash ^b
Bit-banded on-chip SRAM^c
Reserved non-bit-banded SRAM space
Bit-band alias of 0x2000.0000 through 0x200F.FFFF
Reserved non-bit-banded SRAM space
Watchdog timer
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
SSI0
SSI1
UART0
UART1
UART2
I2C Master 0
I2C Slave 0
I2C Master 1
I2C Slave 1
GPIO Port E
GPIO Port F
GPIO Port G
GPIO Port H
PWM
QEI0
QEI1
Timer0
Timer1
For details on
registers, see
page ...
144
144
-
140
-
243
170
170
170
170
349
349
304
304
304
388
401
388
401
170
170
170
170
471
504
504
216
216
44
November 30, 2007
Preliminary