LM3S2965_0711 Datasheet, PDF (19/574 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2965 Microcontroller
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PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 478
PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 479
PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 480
PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 481
PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 481
PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 481
PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 483
PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 483
PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 483
PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 485
PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 485
PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 485
PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 486
PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 486
PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 486
PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 487
PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 487
PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 487
PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 488
PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 488
PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 488
PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 489
PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 489
PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 489
PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 490
PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 490
PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 490
PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 491
PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 491
PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 491
PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 494
PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 494
PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 494
PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 497
PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 497
PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 497
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 498
PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 498
PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 498
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 499
PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 499
PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 499
Quadrature Encoder Interface (QEI) .......................................................................................... 500
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 505
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 507
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 508
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 509
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 510
November 30, 2007
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Preliminary