TMC428_06 Datasheet, PDF(8/58 Page) List of Unclassifed Manufacturers – Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces

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TMC428_06 Datasheet, PDF (8/58 Pages) List of Unclassifed Manufacturers – Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces

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TMC428 DATASHEET (v. 2.02 / April 26th, 2006)

6 Serial Peripheral Interfaces

The four pins named SCS_C, SCK_C, SDI_C, SDO_C form the serial microcontroller interface of the

TMC428. The communication between the microcontroller and the TMC428 takes place via 32 bit

datagrams of fixed length. Concerning communication, the ÂµC is the master and the TMC428 is the

slave, with the TMC428 in turn being the master for the stepper motor driver daisy chain. Similar to the

microcontroller interface, the TMC428 uses a four wire serial interface for communication with the

stepper motor driver daisy chain. The four pins named SCS_S, SCK_S, SDO_S, SDI_S form the serial

stepper motor driver interface. Stepper motor drivers with parallel inputs can be used in connection

with the TMC428 with some additional glue logic.

6.1 Automatic Power-On Reset

The TMC428 performs an automatic power-on reset. For details see section Power-On-Reset, page

50. The TMC428 cannot be accessed before the power-on-reset is completed and the clock is stable.

All register bits are initialized with â0â during power on reset, except the SPI clock pre-divider clk2_div

(see section 9.7, page 29) that is initialized with 15.

6.2 Serial Peripheral Interface for ÂµC

The serial microcontroller interface of the TMC428 behaves as a simple 32 bit shift register. It shifts

serial data SDI_C in with the rising edge of the clock signal SCK_C and copies the content of the 32 bit

shift register with the rising edge of the selection signal nSCS_C into a buffer register. The serial

interface of the TMC428 immediately sends back data read from registers or read from internal RAM

via the signal SDO_C. The signal SDO_C can be sampled with the rising edge of SCK_C, but SDO_C

becomes valid at least four CLK clock cycles after SCK_C becomes low as outlined in the timing

diagram Figure 6-1. For detailed timing parameters see Table 6-1, page 10. The SPI signals from the

ÂµC interface may be asynchronous to the clock signal CLK of the TMC428.

Because of on-the-fly processing of the input data stream, the serial microcontroller interface of the

TMC428 requires the serial data clock signal SCK_C to have a minimum low / high time of three clock

cycles. The data signal SDI_C driven by the microcontroller has to be valid at the rising edge of the

serial data clock input SCK_C. The maximum duration of the serial data clock period is unlimited.

While the ÂµC interface of the TMC428 is idle, the SDO_C signal is the (active low) interrupt status nINT

of the integrated interrupt controller of the TMC428. The timing of the multiplexed interrupt status

signal nINT is characterized by the parameters tIS an tSI (see Table 6-1, page 10).

Hint: If the microcontroller and the TMC428 work on different clock domains that run asynchronous to

each other, the timing of the SPI interface of the microcontroller should be made conservative in the

way that the length of one SPI clock cycle equals 8 or more clock cycles of the TMC428 clock CLK.

This make the system robust concerning frequency drift, jitter, etc.

tCLK

tDATAGRAMuC

CLK

tSUCSC tHDCSC tSCKCL tSCKCH

tHDCSC tSUCSC

nSCS_C

SCK_C

SDI_C

SDO_C

nINT

tSD

sdi_c_bit#31

sdi_c_bit#30 . . . sdi_c_bit#1

sdi_c_bit#0

tPD

sdo_c_bit#31 sdo_c_bit#30 ... sdo_c_bit#1

sdo_c_bit#0

nINT

tIS

tSI

1 x SDI_C sampled

30 x sampled SDI_C

one full 32 bit datagram

1 x SDI_C sampled

Figure 6-1: Timing diagram of the serial ÂµC interface

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