TMC428_06 Datasheet, PDF(24/58 Page) List of Unclassifed Manufacturers – Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces

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TMC428_06 Datasheet, PDF (24/58 Pages) List of Unclassifed Manufacturers – Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces

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TMC428 DATASHEET (v. 2.02 / April 26th, 2006)

bit REF_RnL (reference switch Right not Left) defines which switch is the reference switch: If set to â1â,

the right, else (set to â0â) the left one is the reference switch.

The bits contained in ref_conf control the semantic and the actions of the reference/stop switch

modes for interrupt generation as explained later. The stepper motor stops if the reference/stop switch,

which corresponds to the actual driving direction, becomes active. The configuration bits named

DISABLE_STOP_L respectively DISABLE_STOP_R disable these automatic stop functions. If the bit

SOFT_STOP is set, motor stop forced by a reference switch is done within motion parameter limits

while otherwise stopping is abruptly.

Hint: There is a functional difference between reference switches and stop switches. Reference

switches are used to determine a reference position for a stepper motor. Stop switches are used for

automatic stopping a motor when reaching a limit. The signals of switches are processed via the inputs

named REF1, REF2, REF3 might be used as automatic stop switches, reference switches, or both.

32 bit DATAGRAM sent from a ÂµC to the TMC428

33222222222211111111119876543210

1098765432109876543210

ADDRESS

DATA

smda 1 0 1 0

ref_conf

Table 8-5: lp & ref_conf & ramp_mode (rm) data bit positions

8.13 interrupt_mask & interrupt_flags (IDX=%1011)

The TMC428 provides one interrupt register of eight flags for each stepper motor. Interrupt bits are

named INT_<mnemonic>. An interrupt bit can set back to â0â by writing â1â to it. Each interrupt bit can

either be enabled (â1â) or disabled (â0â) individually by an associated interrupt mask bit named

MASK_<mnemonic>. The interrupt flags are forced to â0â if the corresponding mask bit is disabled

(â0â). The bit mapping of the interrupt mask bits and interrupt bits itself is diagrammed in Table 8-7 on

page 25. The interrupt out SDO_C / nINT is set active low â where the interrupt status bit INT is set

active high - when at least one interrupt flag of one motor becomes set. The interrupt mask enables or

disables each interrupt mask individually. So, if the interrupt status is inactive, nINT is high (â1â) and

INT is low ('0'). The interrupt status is mapped to the most significant bit (31) of each datagram sent

back to the ÂµC (see Table 6-4, page 12) and it is only available at the SDO_C / nINT pin of the

TMC428 if the pin nSCS_C is high.

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