TMC428_06 Datasheet, PDF (49/58 Pages) List of Unclassifed Manufacturers – Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces

TMC428 DATASHEET (v. 2.02 / April 26^th, 2006)
49
16 On-Chip Voltage Regulator
The on-chip voltage regulator delivers a 3.3V supply for the chip core. An external 470 nF ceramic
capacitor has to be connected between the V33 pin (see Figure 16-1, page 49) and ground, with
connections as short as possible. Additionally, an external 100 nF ceramic capacitor (CBLOCK) has to
be connected between pin V5 and ground– with connections as short as possible –in 5V operational
mode. In 3.3V operational mode an external 100 nF ceramic capacitor (see Figure 16-1, page 49) is
necessary only between pin V33 and ground, with connections as short as possible.
Symbol
TRANGEREG
VDD5REG
CBLOCK
VDD3REG
ICCNLREG
tSREG
tSREGC
TDRFT
VRIPPLE
CREG
COPT
PSRRDC
Parameter
Conditions
Min Typ Max Unit
Temperature range
Industrial
-40
85
°C
Supply voltage vdd5
5 V Operational Mode
4.5
5
5.5
V
Block capacitor
5 V Operational Mode, x7r ceramic capacitor
100
nF
Supply voltage vdd3
3.3 V Operational Mode
2.9 3.3 3.6
V
Current consumption no load
50 100
µA
Startup time
no external capacitor connected
20
µs
Startup time
C_load = 470 nF
150
µs
Temperature drift
300 ppm / °C
Ripple on vdd3
With ripple over 50 mV the input thresholds
may differ from that specified in the data sheet
100
mV
External capacitor
On V33 pin, x7r ceramic, necessary capacity 33 470
nF
depending on ripple requirements. Using
external capacitor with capacity other than
typical, the ripple should be measured on pin
v33 to be sure that requirements are satisfied.
Optional capacitor
Optional parallel capacitor for additional
470
pF
reduction of high frequency ripple, c0g
ceramic, unnecessary in most cases
power supply ripple DC
rejection
50
dB
Table 16-1: Characteristics of the on-chip voltage regulator
3.3V Operation (CMOS)
nSCS_C
REF1 REF2 REF3
nSCS_S
SDI_C
TMC428
SDO_S
SCK_C
SDO_C _CLK
V33
SCK_S
V5 TEST GND ^SDI_S
+3.3V
100nF ^*
5V Operation (TTL)
nSCS_C
REF1 REF2 REF3
nSCS_S
SDI_C
TMC428
SDO_S
* Capacitors should be placed as
cloase as possible to the chip.
SCK_C
SDO_C _CLK
V33
SCK_S
V5 TEST GND ^SDI_S
Pinns named GND and TEST have to be connected
to ground as close as possible to the chip.
470 nF ^*
Copt
100 nF ^*
The optional capacitor Copt is unnecessary in most cases.
+5 V
Figure 16-1: 3.3V operation (CMOS) vs. 5V operation (TTL)
Copyright © 2004-2006, TRINAMIC Motion Control GmbH & Co. KG