TMC428_06 Datasheet, PDF (10/58 Pages) List of Unclassifed Manufacturers – Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces

TMC428 DATASHEET (v. 2.02 / April 26^th, 2006)
10
CLK
nSCS_S
SCK_S
SDO_S
SDI_S
tCLK
tPD
tPD
tPD
tDATAGRAMdrv
m datagram bits
tSUSCSdrv
tHDSCSdrv
sdo_s_bit#0
sdi_s_bit#0
tCKSL
tCKSH
sdo_s_bit#1
sdi_s_bit#1
sdo_s_bit#n-1
sdi_s_bit#n-1
1 x sampled SDI_S
m x sampled SDI_S
one full stepper motor driver datagram
Figure 6-3: Timing diagram of the serial stepper motor driver interface
sdo_s_bit#n
sdi_s_bit#n
1 x sampled SDI_S
To switch to the next motor, an additional bit called next motor bit (NxM-Bit) is prefixed to the five bit
wide primary signal code words. So, the total data word width is six bit. Each NxM-Bit effects an
increment of an internal stepper motor address until the processing for all stepper motors within the
daisy chain is completed. A parameter called LSMD (last stepper motor driver) defines the total
number of stepper motors within the daisy chain. So, the codes written into the serial interface
configuration RAM area represent the mapping of control signals provided by the micro step units to
control bits of the drivers. It might be noted here, that configuring the serial driver interface is much
easier as it might seem here. It is explained in detail, illustrated by examples below (see section 11
Stepper Motor Driver Datagram Configuration, page 36).
Symbol
Parameter
Min
Typ
tSUCSC
Setup Clocks for nSCS_C
3
tHDCSC
Hold Clocks for nSCS_C
3
tSCKCL
Serial Clock Low
3
tSCKCH
Serial Clock High
3
tSD
SDO_C valid after SCK_C low
2.5
tIS
nINTERRUPT status valid after nSCS_C low 2.5
tSI
SDO_C valid after nSCS_C high
tDAMAGRAMuC Datagram Length
3+3 + 32*6 = 198
tDAMAGRAMuC Datagram Length
12.375
fCLK
Clock Frequency
0
tCLK
Clock Period tCLK = 1 / fCLK
62.5
tPD
CLK-rising-edge-to-Output Propagation Delay
5
Table 6-1: Timing characteristics of the serial microcontroller interface
Max
∞
∞
∞
∞
3.5
4.5
∞
∞
16
∞
Unit
CLK periods
CLK periods
CLK periods
CLK periods
CLK periods
CLK periods
CLK periods
CLK periods
µs
MHz
ns
ns
Symbol
tSUSCSdrv
tHDSCSdrv
tCKSL
tCKSH
tDAMAGRAMdrv
tDAMAGRAMdrv
tPD
Parameter
Datagram Length
Datagram Length @ fCLK = 16
MHz
CLK-rising-edge to Outputs Delay
Min
8
8
8
8
8+8+1*16+8+8=48
3
Typ
Max
Unit
16
256
CLK periods
16
256
CLK periods
16
256
CLK periods
16
256
CLK periods
512+64*512+512= 33792 CLK periods
2112
µs
5
ns
Table 6-2: Timing characteristics of the serial stepper motor driver interface
Copyright © 2004-2006, TRINAMIC Motion Control GmbH & Co. KG