TMC428_06 Datasheet, PDF (38/58 Pages) List of Unclassifed Manufacturers – Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces

TMC428 DATASHEET (v. 2.02 / April 26^th, 2006)
38
datagrams to the stepper motor driver chain. Those datagrams have a random power-on configuration
of the on-chip-RAM. So, before trying to move a motor, the on-chip RAM must be initialized first.
11.2 An Example of a Stepper Motor Driver Datagram Configuration
The following example demonstrates, how to configure the datagram and shows what has to be stored
within the on-chip RAM to represent the desired configuration. That example refers to a driver chain of
three TRINAMIC stepper motor drivers of type TMC236, TMC239, TMC246, TMC249. From the
TMC428 datagram configuration point of view, there is no difference between these drivers. All these
drivers have a serial interface of 12 bits length. The configuration is as follows. For the first and the
second stepper motor driver of the chain the fast decay control bit (FD_A, FD_B) is fixed to ‘0’. For the
third driver the fast decay control bit are used. The corresponding content of the configuration on-chip
RAM is outlined in Table 11-2. The sequence to be sent to the TMC428 for this configuration is
outlined in Table 11-3.
Hint: The stepper motor driver datagram configuration can be accessed at any time without conflict,
e.g. to changed between a configuration using fast decay versus a configuration where fast decay is
disabled.
position
driver NxM TMC428
RAM
RAM
TMC428
within
bit
signal
address
data
mnemonic of
datagram
code
primary signal
0
0
$10
$00
$10 Zero
→
1
0
$05
$01
$05 DAC_A_5
→
2
0
$04
$02
$04 DAC_A_4
→
3
0
$03
$03
$03 DAC_A_3
→
4
0
$02
$04
$02 DAC_A_2
→
5
0
$06
$05
$06 PH_A
→
6
0
$10
$06
$10 Zero
→
7
0
$0D
$07
$0D DAC_B_5
→
8
0
$0C
$08
$0C DAC_B_4
→
9
0
$0B
$09
$0B DAC_B_3
→
10
0
$0A
$0A
$0A DAC_B_2
→
11
1
$0E
$0B
$2E PH_B
→
12
0
$10
$0C
$10 Zero
→
13
0
$05
$0D
$05 DAC_A_5
→
14
0
$04
$0E
$04 DAC_A_4
→
15
0
$03
$0F
$03 DAC_A_3
→
16
0
$02
$10
$02 DAC_A_2
→
17
0
$06
$11
$06 PH_A
→
18
0
$10
$12
$10 Zero
→
19
0
$0D
$13
$0D DAC_B_5
→
20
0
$0C
$14
$0C DAC_B_4
→
21
0
$0B
$15
$0B DAC_B_3
→
22
0
$0A
$16
$0A DAC_B_2
→
23
1
$0E
$17
$2E PH_B
→
24
0
$07
$18
$07 FD_A
→
25
0
$05
$19
$05 DAC_A_5
→
26
0
$04
$1A
$04 DAC_A_4
→
27
0
$03
$1B
$03 DAC_A_3
→
28
0
$02
$1C
$02 DAC_A_2
→
29
0
$06
$1D
$06 PH_A
→
30
0
$0F
$1E
$0F FD_B
→
31
0
$0D
$1F
$0D DAC_B_5
→
32
0
$0C
$20
$0C DAC_B_4
→
33
0
$0B
$21
$0B DAC_B_3
→
34
0
$0A
$22
$0A DAC_B_2
→
35
1
$0E
$23
$2E PH_B
→
With LSMD = %10 the (third) NxM bit at address $23 (position 35) finishes the datagram transmission
TMC23x /
TMC24x
Bit Name
MDA
CA3
CA2
CA1
CA0
PHA
MDB
CB3
CB2
CB1
CB0
PHB
MDA
CA3
CA2
CA1
CA0
PHA
MDB
CB3
CB2
CB1
CB0
PHB
MDA
CA3
CA2
CA1
CA0
PHA
MDB
CB3
CB2
CB1
CB0
PHB
Table 11-2: Datagram example and RAM contents for three stepper motor driver chain
Copyright © 2004-2006, TRINAMIC Motion Control GmbH & Co. KG