TMC428_06 Datasheet, PDF (11/58 Pages) List of Unclassifed Manufacturers – Intelligent Triple Stepper Motor Controller with Serial Peripheral Interfaces

TMC428 DATASHEET (v. 2.02 / April 26^th, 2006)
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The timing of the serial driver interface is programmable in a wide range. The clock divider provides 16
up to 512 clock cycles (tCLK) for a serial driver interface data clock period. The default duration of a
clock period (tSCKCL+tSCKCH) of the signal nSCS_S is 16+16=32 clock periods of the clock signal
CLK. The minimal duration of a serial interface clock period (tSCKCL+tSCKCH) is 8+8=16 clock cycles
of signal CLK as outlined in Figure 6-3. Also, the polarities of the signals nSCS_S and SCK_S are
programmable to use driver chips from other vendors with inverted polarities without additional glue
logic. The input SDI_S of the serial driver interface must always be driven to a defined level. So, to
avoid high impedance (‘Z’) at that input pin while the stepper motor driver chain is idle, a pull-up
resistor or a pull-down resistor of 10 KΩ is required at that input.
6.4 Datagram Structure
The microcontroller (µC) communicates with the TMC428 via the four wire (nSCS_C, SCK_C, SDI_C,
SDO_C) serial interface. Each datagram sent to the TMC428 via the pin SDI_C and each datagram
received from the TMC428 via the pin SDO_C is 32 bits long. The first bit sent is the MSB (most
significant bit named sdi_c_bit#31 at Figure 6-1). The last bit sent is the LSB (least significant bit
named sdi_c_bit#0 in Figure 6-1). During reception of a datagram, the TMC428 immediately sends
back a datagram of the same length to the microcontroller. This datagram is the result of the request
from the microcontroller.
With each 32 bit wide datagram the microcontroller sends to the TMC428, it simultaneously receives a
32 bit wide datagram. A read request is distinguished from a write request by one datagram bit named
RW. The TMC428 immediately sends back requested read data in the lower 24 datagram bits. Status
bits are sent back in the higher 8 datagram bits. Datagrams sent from the microcontroller to the
TMC428 have the form:
32 bit DATAGRAM sent from µC to the TMC428 via pin SDI_C
33222222222211111111119876543210
1098765432109876543210
ADDRESS
DATA
Table 6-3 : 32 bit DATAGRAM structure sent from µC (MSB sent first)
The 32 bit wide datagrams sent to the TMC428 are assorted in four groups of bits: RRS (register RAM
select) selecting either registers or on-chip RAM; ADDRESS bits addressing memory within the
register set or within the RAM area; RW (read / not write (RW=1 : read / RW=0 : write)) bit
distinguishing between read access and write access; DATA bits for write access– for read access
these bits are don’t care and should be set to ‘0‘. Different internal registers of the TMC428 have
different lengths. So, for some registers only a subset of these 24 data bits is used. Unused data bits
should be set to ‘0‘ for clearness. Some addresses select more than a single register mapped together
into the 24 data bit space.
The 32 bit wide datagrams received by the µC from the TMC428 contain two groups of bits: STATUS
BITS and DATA BITS. The status bits, sent back with each datagram, carry the most important
information about internal states of the TMC428 and the settings of the reference switches. These
datagrams have the form:
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