CT8022 Datasheet, PDF (61/194 Pages) List of Unclassifed Manufacturers – VOIP/VON G.723.1, G279AB TRUESPEECH CO-PROCESSOR

Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
Terminating Record
1. Host writes IDLE = 0000H command or STOP RECORD = 5120H command to the Software Control Register.
2. CT8022 terminates record and clears RX Ready if set (in Hardware Status Register).
3. CT8022 writes status response to Software Status Register.
4. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response
from the Software Status Register. This clears the STATUS READY bit.
Note: After writing the Idle or Stop Record command to terminate recording, the Host should not attempt
to access the Host Receive Data Buffer Access Port even if the RX Ready bit is set.
Example 2: TrueSpeech 5.3 Record via Host Receive Data Buffer Access Port - Host Interrupt
This example shows how to start recording using TrueSpeech 5.3 with data transfers performed via the Host Receive
Data Buffer Access Port. The Host controller performs all data transfers in this example. The Host uses an interrupt
service routine (ISR) to transfer data.
Starting Record
1. CT8022 is in IDLE state or PLAYBACK.
2. Host checks for CONTROL READY state in Hardware Status Register.
3. Host selects TrueSpeech 5.3 recording by writing the Select TrueSpeech Record Rate command = 5132H to the
Software Control Register.
4. CT8022 responds via the Software Status Register
5. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response
from the Software Status Register. This clears the STATUS READY bit.
6. Host selects Poll Sync Mode for record using the command 5102H.
7. CT8022 responds via the Software Status Register.
8. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response
from the Software Status Register. This clears the STATUS READY bit.
9. Host selects Record by issuing the RECORD C1 command = 1C03H via the Software Control Register. This
also informs the CT8022 that data transfers will occur via the Host Receive Data Buffer Access Port (TFR
Mode = [binary] 11 ).
10. CT8022 performs internal synchronization then responds with the RECORD S1 status response after a delay of
up to 2 speech frame periods.
11. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response
from the Software Status Register. This clears the STATUS READY bit.
12. Host sets up an ISR to service interrupts from the CT8022.
13. Host programs the Hardware Control Register to generate an interrupt from the CT8022 on the RX Ready
condition by writing 0401H ( Master Enable set, RX Ready IE set).
13. The CT8022 is now in record mode. The CT8022 will produce a compressed speech frame every 30ms
(assuming the base frame size is set to 240). The following sequence is used by the Host ISR to transfer each
compressed speech data frame from the CT8022 to the Host:
a. Host gets interrupt from CT8022 (optionally checks that RX Ready is set).
b. Host reads 10 words (for TrueSpeech 5.3) from the Host Receive Data Buffer Access Port.
Terminating Record
1. Host disables interrupts from the CT8022 by writing 0000H to the Hardware Control Register.
2. Host writes IDLE = 0000H command or STOP RECORD = 5120H command to the Software Control Register.
3. CT8022 terminates record and clears RX Ready if set (in Hardware Status Register).
4. CT8022 writes status response to Software Status Register.
5. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response
from the Software Status Register. This clears the STATUS READY bit.
Note: After writing the IDLE or STOP RECORD command to terminate recording, the Host should not
attempt to access the Host Receive Data Buffer Access Port even if the RX Ready bit is set.
CT8022A11AQC FW Revision 0118
DSP GROUP, INC., 3120 SCOTT BOULEVARD
61
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.