CT8022 Datasheet, PDF (12/194 Pages) List of Unclassifed Manufacturers – VOIP/VON G.723.1, G279AB TRUESPEECH CO-PROCESSOR

TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
Pin Names
IRQ/
(IRQN)
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
BSEL
DRDN
DWRN
PRDN
PWRN
CREADN
BRDN
DCSN
(SRAMCSN)
RSTN
(RESETN)
12
Pin Nrs
121
Type
OC
Function
Interrupt Request. Open collector output (requires external pull-up resistor with min
value 1K ohm). This signal is asserted to indicate an interrupt request to the Host
controller.
78
I/O/Z External Memory Data Bus used to interface to external memory. The CT8022
79
requires an external memory configured as 8K or 32K x 16. The 32K x 16
80
configuration is required for support of downloadable external software modules.
81
84
85
86
87
90
91
92
93
96
97
98
99
46
O/Z External Memory Address Bus used to interface to external memory. Note that the
47
CT8022 is a 16-bit device and the address lines indicate access to 16-bit data words.
48
49
52
53
54
55
58
59
60
61
64
65
66
67
43
O/Z Byte Select. Used in CT8022 designs to access external byte wide memory.
72
O/Z External Data Memory Read. Active Low, used to indicate a data read cycle from
external data memory
73
O/Z External Data Memory Write. Active Low, used to indicate a data write cycle to
external data memory.
68
O/Z External program memory read.
69
O/Z External program memory write.
100
O/Z Combined external program read and data read. This is equivalent to logical AND
combination of PRDN and DRDN.
This pin is asserted (active low) whenever an external data or program read cycle is
executed.
Compatibility Note: The CT8020 does not provide this pin.
Use this pin instead of DRDN to create a single external combined program/data
address space to support external downloadable software modules with the CT8022.
75
O/Z Reserved - NC (do not connect)
74
O/Z External data SRAM chip select. Active low. This signal is asserted during external
data access only. This signal is not asserted during external program memory read or
write accesses.
14
I
Reset signal. Active Low, the pin is driven low to reset the device. Note - this pin is
not a TTL input. VIH (max) = 4.5 volts. VIL (min) = 1.3 volts.
The reset pulse should be a minimum of 10 CLKOUT periods in width (after Vcc has
stabilized and a clock is present at XOUT)
DSP GROUP, INC., 3120 SCOTT BOULEVARD
CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.