CT8022 Datasheet, PDF (169/194 Pages) List of Unclassifed Manufacturers – VOIP/VON G.723.1, G279AB TRUESPEECH CO-PROCESSOR

Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
11 CT8022 CODEC Interface Timing and AC Specification
11.1 Short Frame Sync
SCLK
FSYNC
DR0,DR1
t1
t2
t8
DX0,DX1
1
2
3
4
5
6
7
8
t3
Bit 7
Bit 7
t4
Bit 6
Bit 6
Bit 5 Bit 4
t5
Bit 5 Bit 4
Bit 3 Bit 2
t6
Bit 3 Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
t7
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
Description
Output delay from rising edge of
SCLK to rising edge of FSYNC
(master mode only)
FSYNC setup time before falling
edge of SCLK (slave mode only)
FSYNC hold time after falling edge
of SCLK.
(slave mode only)
SCLK rising edge to data output
valid
data in setup prior to falling edge of
SCLK
data in hold time after falling edge
of SCLK
data out tri-state after final falling
edge of SCLK
FSYNC width
(master mode only)
SCLK duty cycle
Min
0 ns
50 ns
100 ns
0 ns
30 ns
30 ns
0.25 * SCLKPERIOD
(122 ns at 2.048 MHz)
45%
Max
50 ns
30 ns
0.5 * SCLKPERIOD
(244 ns at 2.048 MHz)
1 SCLK period (nominal)
55%
Notes:
1. SCLK is 2.048 MHz nominal; SCLKPERIOD is 488 ns nominal.
2. Timing diagram shows 8-bit mode only. In 16-bit mode, 16 bits of transmit data are shifted into and out
of the CT8022. Bit 15 occurs first.
CT8022A11AQC FW Revision 0118
DSP GROUP, INC., 3120 SCOTT BOULEVARD
169
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.