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CT8022 Datasheet, PDF (40/194 Pages) List of Unclassifed Manufacturers – VOIP/VON G.723.1, G279AB TRUESPEECH CO-PROCESSOR
TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
5 CT8022 CODEC Interface
Version: 1.18
DX0
DR0
47K
Host
SCLK
CT8022
47K
FSYNC
47K
DX1
DR1
47K
CODEC
0
Optional second CODEC for
Full-Duplex Speakerphone
CODEC 1 connects to
microphone and speaker
CODEC
1
Figure 5-1:
CT8022 CODEC Interface Connection
In Master mode, the CT8022 generates the FSYNC and SCLK signals.
In Slave mode, the FSYNC and SCLK signals are generated externally. In slave mode, the CT8022 FSYNC and
SCLK pins are inputs.
Note: During and after reset, the SCLK and FSYNC pins are configured as inputs. As such, they require
external pull-down resistors to ensure that a safe and defined logic level is present.
5.1 CODEC Options
The CT8022 CODEC interface supports the following features:
• CODEC clock master or slave
• 8-bit A-law/µ-law or 16-bit linear CODEC
• Short or Long FSYNC
• Programmable SCLK and FSYNC clock rates
40
DSP GROUP, INC., 3120 SCOTT BOULEVARD
CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.