CT8022 Datasheet, PDF (35/194 Pages) List of Unclassifed Manufacturers – VOIP/VON G.723.1, G279AB TRUESPEECH CO-PROCESSOR

Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
4.5.5.2.1 Transmit Data Buffer Internal Control Register
This is an internal register, and is not accessible by the Host.
0000 0000
(15-8)
TX Ready
(7)
00
(6-5)
Frame Size
(4-0)
TX Ready:
When set to zero, the CT8022 has control of the data buffer and can read any location in
the buffer.
When set to one, the Host has control of the data buffer and may write its contents via the
Host Data Buffer access port.
The Host can check the state of this bit at any time since it is reflected by the TX Ready
bit in the Hardware Status register. The TX Ready bit in the Transmit Data Buffer drives
the TX Ready bit and TXDREQ via the DMA logic.
After reset, this bit is zero.
Frame Size:
The Frame Size field determines the number of words contained in the data buffer. It acts
as the reference input to the Host buffer address comparator.
Address Counter
The 5-bit address counter provides the sequential buffer access address for access by the Host via the Host Data
Buffer access port. The address counter is reset to zero when the CT8022 writes a 1 to the TX Ready bit of the
internal control register causing control of the buffer to transfer to the Host. Each time the Host accesses the upper
byte of the Host Data Buffer access port the address counter increments by 1.
The data buffer access port is only physically 8-bits wide. When a Host processor accesses to this port, the byte
select address line HSTAB0 is valid and can be used to select the byte accessed. When access is by a DMA
controller, the address decode which selects the data buffer access port is provided by the TXDACKN signal.
During a DMA cycle, the HSTAB3-0 address bits are not valid. Generation of an internal HSTAB0 is thus required
to select the byte accessed. A simple toggle mechanism, which changes state on each DMA access, performs this
function. The DMA byte select toggle is set to zero each time the TX Ready bit changes from a zero to a one (this
also clears the main address counter).
A separate DMA byte select toggle is required for transmit and receive.
Comparator
The 5-bit comparator is active only when the Host has control (the TX Ready bit is set). The comparator compares
the value in the address counter with the value in the Frame Size field. If the values are not equal, the Host continues
to have access to the data buffer. When the values become equal (after the last Host access), the TX Ready bit is
reset, transferring control back to the CT8022.
Transferring Data From Host To CT8022
The CT8022 determines the size of the data frame to be transferred by a protocol with the Host. At the beginning of
data transfer, the TX Ready bit will be zero. The CT8022 then programs the Frame Size and sets the TX Ready bit
(in the same write cycle). This causes the TX Ready bit visible in the Hardware Status Register to be set. The Host
discovers that the TX Ready bit is set (by polling or interrupt). The Host then writes Frame Size words into the Host
Transmit Buffer Access Port. After each word is written, the address counter is incremented. When the Host writes
the last word, the address counter is incremented, and matches the Frame Size value. This is detected by the
comparator, which causes the TX Ready bit to be cleared. The CT8022 discovers that it has access to the data buffer
and reads the buffer contents, transferring them to the CT8022’s local RAM. This process is repeated to transfer the
next frame.
For DMA transfers, the TX Ready bit drives the state of the DMA Request signal. When TX Ready is set, the DMA
request is asserted. When the buffer becomes full, and buffer control automatically returns to the CT8022, the TX
Ready bit is cleared and the DMA Request signal is de-asserted.
CT8022A11AQC FW Revision 0118
DSP GROUP, INC., 3120 SCOTT BOULEVARD
35
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.