ALS300 Datasheet, PDF (53/66 Pages) List of Unclassifed Manufacturers – Media Audio Controller SPEC

Avance Logic Inc.
ALS300
When ALS300 start DRAM data transfer, DA[20..2] is the starting address of the DRAM
memory space. This address will increase automatically during the transfer period. SW should
update this register content before the beginning of next block transfer.
GCR8E Default : XXXXXXXXh Music/Voice volume
Bit Type
Function
31:27 R/W Music-Left volume in 1.5Db step , 00h : 0dB , 1Fh : -46dB
26:24
Reserved
23:19 R/W Music-Right volume in 1.5Db step , 00h : 0dB , 1Fh : -46dB
18:16
Reserved
15:11 R/W Voice-Left volume in 1.5Db step , 00h : 0dB , 1Fh : -46dB
10:8
Reserved
7:3
R/W Voice-Right volume in 1.5Db step , 00h : 0dB , 1Fh : -46dB
2:0
Reserved
nSW should set a default volume after system reset.
GCR8F Default : XXXXXXXXh Modem I/O
Bit Type
Function
31:16
W Modem-Out data bit 15~0
15:0
R Modem-In data bit 15~0
GCR90 Default : XX5A0000h
Test mode register
Bit Type
Function
31:24 R/W Reserved
23:22 R/W RC oscillator output divider 00:2 01:4 10:8 11:16
21:20 R/W VCO V-I stage resistor select 00:5.2K 01:4.5K 10:3.7K 11:3K
19
R/W RC oscillator input current control 0:30u 1:45u
18
R/W VCO input current control 0:30u 1:45u
17:16 R/W Band Gap resister control 00:2.5K 01:2.2K 10:1.9K 11:1.6K
15:8 R/W SB test mode register (Normal = 00h)
7:6
R/W Wave engine test mode register
5
R/W PLL test (PLLTEST) 0 : 14.318M/256 1: 2M/32
4:0
R/W Wave engine test mode register (Normal = 00h)
nPLLTEST 0
XCLK output 14.318M/256 clock
1
XCLK output OSC2 clock (2M/32 Hz)
GCR91 Default : 00FFFFFFh DMA 0 starting address
Bit Type
Function
31:24
Reserved
23:0
R DMA channel 0 starting address SA0[23..0]
nStuff SA0[31..24] with 0 when implemented.
GCR92 Default : 0000FFFFh
DMA 0 mode register and base byte count
Bit Type
Function
31:22
Reserved
21
R Address increment/decrement select. 0 : increment 1 : decrement
20
R Auto-initialization enable 0 : Disable 1 : Enable
19:18
R Transfer mode 01 : Write 10 : Read Others : Reserved
17:16
Reserved
15:0
R DMA channel 0 base byte count BBC0[15..0]
nWrite transfer
ALS300 → Memory
Read transfer
ALS300 ← Memory
GCR93 Default : 00FFFFFFh DMA 1 starting address
Bit Type
Function
31:24
Reserved
23:0
R DMA channel 1 starting address SA1[23..0]
nStuff SA1[31..24] with 0 when implemented.
GCR94 Default : 0000FFFFh DMA 1 mode register and base byte count
Bit Type
Function
53