ALS300 Datasheet, PDF (49/66 Pages) List of Unclassifed Manufacturers – Media Audio Controller SPEC

Avance Logic Inc.
ALS300
Bit Type
Function
7
R INDX status 0 : Ready for AC97 mixer access
1 : AC97 is busy
6
R DIN status 0 : Empty
1 : AC97 mixer data is available
5
R MOUT status 0 : AC97 is ready for Modem-Out transfer
1 : AC97 Modem-Out is busy
4
R MPU401 IRQ flag 0 : No IRQ 1 : IRQ generated (For D version only)
3
R PCILO/PCIRO FIFO status 0 : empty 1 : non-empty
2
R PCILI/PCIRI FIFO status 0 : empty 1 : non-empty
1
R MICIN FIFO status 0 : empty 1 : non-empty
0
R DRAM FIFO status 0 : empty 1 : non-empty
nAn IO-Write to AC97-ACCESS with bit 31=1 will clear bit 6.
oRead IOBASE+4~7 will clear bit 4 automatically. (For D Version)
IRQ-STATUS Default : 00h
IOBASE + 07h
Bit Type
Function
7
R/W SB/MPU IRQ flag : 0 : Normal 1 : IRQ generated
6
R/W DRAM IRQ flag : 0 : Normal 1 : IRQ generated
5
R/W SB-Mixer IRQ flag : 0 : Normal 1 : IRQ generated
4
R/W MICIN IRQ flag : 0 : Normal 1 : IRQ generated
3
R/W PCI-Play IRQ flag : 0 : Normal 1 : IRQ generated
2
R/W PCI-Rec IRQ flag : 0 : normal 1: IRQ generated
1
R/W Modem-In IRQ flag : 0 : Normal 1 : IRQ generated
0
R/W Ring-In IRQ flag : 0 : Normal 1 : IRQ generated
nWrite this register with “1” will clear the corresponding IRQ flag.
oWrite this register with “0” will keep the corresponding IRQ flag.
When bit 7 is set, TSR should read MX82 to identify the requesting device. Write 1 to this
bit will clear the flag too. TSR should acknowledge the IRQ by access acknowledge port
in “SB logic”. Note that IRQ request from SB core is routed to INTA# directly. Bit 7 is
a flag only
„The MPU401 IRQ status located at different register for different version.
Version
Location
Acknowledge
A
IRQ-STATUS bit 7
Write IRQ-STSTUS with bit 7 as 1
C
IRQ-STATUS bit 7
Write IRQ-STSTUS with bit 7 as 1
D
AC97-STATUS bit 4
Read AC97-STSTUS once
E,F,G
IOBASE+E bit 4
Read IOBASE+C~E
GCR/RAM-DATA
Default : XXXXXXXXh IOBASE + 08-0Bh
Bit Type
Function
31:0 R/W GCR/Wave engine RAM data
GCR/RAM-Index
Default : XXh
IOBASE + 0Ch
Bit Type
Function
7
R/W GCR/Wave engine select 0 : Wave engine RAM 1 : GCR
6:0
R/W GCR/Wave engine RAM index
EXT-IRQ-STATUS Default : 00h
IOBASE + 0Eh
Bit Type
Function
7:5
Reserved
4
R MPU401 IRQ flag : 0 : Normal 1 : IRQ generated
(implemented for version latter than E)
3:1
Reserved
0
R FFLP (Internal Flip-Flop , implemented for version latter than F)
‚Read IOBASE+0Eh will clear bit 4 automatically
ƒBit 0 will use as low/high byte pointer when driver take IO trapping skill.
ALS300 Global Control Register Array :
Index Port : GCR/RAM-Index
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