ALS300 Datasheet, PDF (52/66 Pages) List of Unclassifed Manufacturers – Media Audio Controller SPEC

Avance Logic Inc.
ALS300
qIt spend 12 clocks of BITCLK (12.288MHz) to switch between DRAM access mode 1 and
mode 2. The programmer should wait until the state transition is complete.
GCR8C
Default XXXX0011h
Miscellaneous control
Bit Type
Function
31:30
Reserved
29
R 279/A79 snoop control 0 : Enable 1 : Disable
28
R PCI/SB# status 1 : PCI wave 0 : SB wave
27
Reserved
26
R ALS300 clock source 0 : Internal PLL 1 : External crystal
25
R PnP port IOEN gating control 0 : No gating 1 : gating
24
R PnP emulation H/W control bit 0 : Enable 1 : Disable
23
R/W PLL or crystal oscillator control (VCO-OSCEN#) 0:Enable(Default) 1:Disable
22
R/W RC oscillator control (RCCLKEN) 0:Disable(Default) 1:Enable
21
R/W Music mute control (MMUTE#) 1 : Normal 0 : Mute (Default : 1)
20
R/W Voice mute control (VMUTE#) 1 : Normal 0 : Mute (Default : 1)
19:16
R Chip revision number
15
R/W INTA# mask control
0
Enable IRQ output
1
Disable IRQ output (Drive INTA# to inactive state)
Version F or latter :
1
Enable IRQ output
0
Disable IRQ output (Drive INTA# to inactive state)
14
R/W AC97 interface loop-back control (ACLB)
0 : Normal 1 : Loop-back (AC serial output → AC serial input)
13
R/W FIFO loop-back control
0 : Disable 1 : Enable (PCILO→PCILI,PCIRO→PCIRI,PCILO→MICIN)
12
R/W MIN IRQ control 0 : Disable 1 : Enable
11
R/W Ring-In IRQ control 0 : Disable 1 : Enable
10
R/W Digital sum control
0
PCM_sum = PCM_voice + PCM_music
1
PCM_sum = PCM_voice/2 + PCM_music/2
9
R/W Legacy-DMA read control 0 : disable (Default) 1 : Enable
8
R/W Special Data latch control 0 : Normal 1 : SiS5513
7
R Level latch from HOOK when system reset.
6:5
R/W AC97 reset mode select
00 : Normal 01 : Warm reset 10 : Cold reset 11 : Reserved
4
R/W PCM playback mute control 0 : mute 1 : unmute
3
R/W HOOK output capability control 0 : Float 1 : Drive bit 2 to pad
2
R/W Data drived to HOOK
1
R Synthesizer MUX status (WVE/FM#)
1 : Internal Wave engine 0 : FM synthesizer
0
R/W Wave engine mute control (WMUTE#) 0 : mute 1 : Normal
nChip-ID will increase by 1 when chip tape-out.
oWVEREQ low-go-high edge will select wave engine as musical synthesizer.
pActually the PnP emulation control signal ,PNPEN, is
PNPEN = BOND & (!GCR8C.24&GCR8C.29)
qWhen GCR8C.5 or GCR8C.6 is set, it will be cleared when AC97 reset operation is complete.
rGCR8C.24 is latched from DQ0 when system reset.
GCR8C.25 is latched from DQ1 when system reset.
GCR8C.26 is latched from DQ2 when system reset.
GCR8D Default : 00XXXXXXh DRAM address of mode 2 access
Bit Type
Function
31:21
Reserved
20:2 R/W DRAM address DA[20..2] (Byte address)
1:0
R Read as 0
52