ALS300 Datasheet, PDF (24/66 Pages) List of Unclassifed Manufacturers – Media Audio Controller SPEC

Avance Logic Inc.
ALS300
Bit 3
Bit 2
Bit 1
Bit 0
001 400us
…
110 900us
111 1000us
Reserved
FIFO CRC check control
0
Normal
1
Clear CRC-32 shift register contents.
Reserved
0
disable SB16 E3 command
1
enable SB16 E3 command
When CR3A.7=1(Game-Pad mode), ALS300 will drive GD0 to low. When SW write port
201h, ALS300 will release it for a period defined in CR3A.6~4 and drive it to low again until
next IO write 201h. For other operation, digital Game-Port is identical to analog Game-Port.
CR3B
CRC-32 Byte 0
Default : 00h
Bit 7~0
CRC-32 bit 7~0
CR3C
CRC-32 Byte 1
Default : 00h
Bit 7~0
CRC-32 bit 15~8
CR3D
CRC-32 Byte 2
Default : 00h
Bit 7~0
CRC-32 bit 23~16
CR3E
CRC-32 Byte 3
Default : 00h
Bit 7~0
CRC-32 bit 31~24
CR3F
SCRACH
8 bit read/write register
Default 00h
Bit 7..0 X
dummy read/write bit for s/w switch
Plug And Play Register:
PNPy-xx
Device y PnP index xx register
PNPxx
Card level PnP index xx register
Sound Blaster Configuration
PNP0-30
Bit
7:1
0
Default :00h Device control
Type
Reserved , read as 0
R/W Device 0 control, 0 : Disable
Function
1 : Enable
PNP0-31
Bit
7:2
1
0
PNP0-60
Bit
7:2
1:0
PNP0-61
Bit
7:4
3:0
Default : 00h IO check control
Type
Function
Reserved , read as 0
R/W IO range check control, 0 : Disable 1 : Enable
R/W IO range check return data 0 : 0xaa 1 : 0x55
Default : 00h Device 0 Base address high byte
Type
Function
Reserved , read as 0
R/W SBBASE[9..8]
Default : 00h Device 0 Base address low byte
Type
Function
R/W SBBASE[7..4]
Reserved, read as 0
24