VS1002D Datasheet, PDF (47/54 Pages) List of Unclassifed Manufacturers – MP3 AUDIO CODEC

VLSI
Solution ^y
VS1002d
VS1002D
10. VS1002D REGISTERS
10.12.3 Configuration TIMER ENABLE
Name
TIMER EN T1
TIMER EN T0
TIMER ENABLE Bits
Bits Description
1 Enable timer 1
0 Enable timer 0
10.12.4 Timer X Startvalue TIMER Tx[L/H]
The 32-bit start value TIMER Tx[L/H] sets the initial counter value when the timer is reset. The timer
interrupt
frequency
f_t
=
f_i
c+1
where
f_i
is
the
master
clock
obtained
with
the
clock
divider
(see
Chap-
ter 10.12.2 and c is TIMER Tx[L/H].
Example: With a 12 MHz master clock and with TIMER CF CLKDIV=3, the master clock f_i = 3M Hz.
If
TIMER
TH=0,
TIMER
TL=99,
then
the
timer
interrupt
frequency
f_t
=
3M Hz
99+1
=
30kH z .
10.12.5 Timer X Counter TIMER TxCNT[L/H]
TIMER TxCNT[L/H] contains the current counter values. By reading this register pair, the user may get
knowledge of how long it will take before the next timer interrupt. Also, by writing to this register, a
one-shot different length timer interrupt delay may be realized.
10.12.6 Interrupts
Each timer has its own interrupt, which is asserted when the timer counter underflows.
Version 1.0, 2005-04-27
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