VS1002D Datasheet, PDF (39/54 Pages) List of Unclassifed Manufacturers – MP3 AUDIO CODEC

VLSI
Solution ^y
VS1002d
VS1002D
10. VS1002D REGISTERS
10.6 DAC Registers
Reg
0xC013
0xC014
0xC015
0xC016
Type
rw
rw
rw
rw
Reset
0
0
0
0
DAC registers, prefix DAC
Abbrev[bits]
Description
FCTLL
DAC frequency control, 16 LSbs.
FCTLH[4:0]
Clock doubler + DAC frequency control MSbs.
LEFT
DAC left channel PCM value.
RIGHT
DAC right channel PCM value.
Every fourth clock cycle, an internal 26-bit counter is added to by DAC FCTLH[3:0] × 65536 + DAC FCTLL.
Whenever this counter overflows, values from DAC LEFT and DAC RIGHT are read and a DAC inter-
rupt is generated.
If DAC FCTL[4] is 1, the internal clock doubler is activated.
10.7 GPIO Registers
Reg
0xC017
0xC018
0xC019
Type
rw
r
rw
Reset
0
0
0
GPIO registers, prefix GPIO
Abbrev[bits]
Description
DDR[3:0]
Direction.
IDATA[3:0]
Values read from the pins.
ODATA[3:0]
Values set to the pins.
GPIO DIR is used to set the direction of the GPIO pins. 1 means output. GPIO ODATA remembers its
values even if a GPIO DIR bit is set to input.
GPIO registers don’t generate interrupts.
Note: Bits 2 and 3 of GPIO DDR and GPIO ODATA are switched in prototypes VS1002b and VS1002c.
Thus, for example, writing 8 to both registers will set pin GPIO2 to 1 instead of GPIO3.
Version 1.0, 2005-04-27
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