VS1002D Datasheet, PDF (18/54 Pages) List of Unclassifed Manufacturers – MP3 AUDIO CODEC

VLSI
Solution ^y
VS1002d
VS1002D
7. SPI BUSES
7.4.3 SDI in VS1001 Compatibility Mode
BSYNC
SDATA
DCLK
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4: BSYNC Signal - one byte transfer.
When VS1002d is running in VS1001 compatibility mode, a BSYNC signal must be generated to ensure
correct bit-alignment of the input bitstream. The first DCLK sampling edge (rising or falling, depending
on selected polarity), during which the BSYNC is high, marks the first bit of a byte (LSB, if LSB-first
order is used, MSB, if MSB-first order is used). If BSYNC is ’1’ when the last bit is received, the receiver
stays active and next 8 bits are also received.
BSYNC
SDATA
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
DCLK
Figure 5: BSYNC Signal - two byte transfer.
7.5 Serial Protocol for Serial Command Interface (SCI)
7.5.1 General
The serial bus protocol for the Serial Command Interface SCI (Chapter 8.5) consists of an instruction
byte, address byte and one 16-bit data word. Each read or write operation can read or write a single
register. Data bits are read at the rising edge, so the user should update data at the falling edge. Bytes are
always send MSb firrst.
The operation is specified by an 8-bit instruction opcode. The supported instructions are read and write.
See table below.
Name
READ
WRITE
Instruction
Opcode
0b0000 0011
0b0000 0010
Operation
Read data
Write data
Note: After sending an SCI command, it is not allowed to send SCI or SDI data for 5 microseconds.
Version 1.0, 2005-04-27
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