VS1002D Datasheet, PDF (29/54 Pages) List of Unclassifed Manufacturers – MP3 AUDIO CODEC

VLSI
Solution ^y
VS1002d
VS1002D
8. FUNCTIONAL DESCRIPTION
Also, with speeds lower than 24.576 MHz all sample rates and bitstream widths are no longer available.
Setting the MSB of SCI CLOCKF to 1 activates internal clock-doubling. A clock of upto 15 MHz may
be doubled depending on the voltage provided to the chip.
Note: SCI CLOCKF must be set before beginning decoding audio data; otherwise the sample rate will
not be set correctly.
Note: Unlike with VS1011, SCI CLOCKF only needs to be written to after a hardware reset.
Example
1:
For
a
26
MHz
clock
the
value
would
be
26000000
2000
=
13000.
Example 2: For a 13 MHz external clock and using internal clock-doubling for a 26 MHz internal
frequency,
the
value
would
be
0x8000
+
13000000
2000
=
39268.
Example
3:
For
a
24.576
MHz
clock
the
value would
be
either
24576000
2000
=
12288,
or
just
the
default
value 0. For this clock frequency, SCI CLOCKF doesn’t need to be set.
8.6.5 SCI DECODE TIME (RW)
When decoding correct data, current decoded time is shown in this register in full seconds.
The user may change the value of this register. However, in that case the new value should be written
twice.
SCI DECODE TIME is reset at every software reset.
8.6.6 SCI AUDATA (RW)
When decoding correct data, the current sample rate and number of channels can be found in bits 15..1
and 0 of SCI AUDATA, respectively. Bits 15..1 contain the sample rate divided by two, and bit 0 is 0 for
mono data and 1 for stereo. Writing to this register will change the sample rate on the run to the number
given.
Example: 44100 Hz stereo data reads as 0xAC45 (44101).
8.6.7 SCI WRAM (RW)
SCI WRAM is used to upload application programs and data to instruction and data RAMs. The start
address must be initialized by writing to SCI WRAMADDR prior to the first call of SCI WRAM. As 16
bits of data can be transferred with one SCI WRAM write, and the instruction word is 32 bits long, two
consecutive writes are needed for each instruction word. The byte order is big-endian (i.e. MSBs first).
After each full-word write, the internal pointer is autoincremented.
Version 1.0, 2005-04-27
29