VS1002D Datasheet, PDF (20/54 Pages) List of Unclassifed Manufacturers – MP3 AUDIO CODEC

VLSI
Solution ^y
VS1002d
VS1002D
7. SPI BUSES
7.6 SPI Timing Diagram
XCS
SCK
tXCSS
0
1
tWL tWH
14
15
16
tXCSH
30
31
tXCS
SI
SO
tZ
tH
tSU
tV
tDIS
Figure 8: SPI Timing Diagram.
Symbol Min
Max Unit
tXCSS
5
ns
tSU
-26
ns
tH
2
XTALI cycles
tZ
0
ns
tWL
2
XTALI cycles
tWH
2
XTALI cycles
tV
2 (+ 25ns¹) XTALI cycles
tXCSH -26
ns
tXCS
2
XTALI cycles
tDIS
10 ns
1 _{25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance.}
Note: As tWL and tWH, as well as tH require at least 2 clock cycles, the maximum speed for the SPI
bus that can easily be used is 1/6 of VS1011’s external clock speed XTALI. Slightly higher speed can be
achieved with very careful timing tuning. For details, see Application Notes for VS10XX.
Note: Negative numbers mean that the signal can change in different order from what is shown in the
diagram.
Version 1.0, 2005-04-27
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