MC3510 Datasheet, PDF (47/75 Pages) List of Unclassifed Manufacturers – Pilot Motion Processor

IOPIL8 2
The CP control starts on IOPIL8 2. The I/O control is generated from ~CPSTRB, ~CPIS, CPSEL
and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 out-enable
the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold times
on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be used for
this interface and the CP.
DSPWA
The CP write control is contained on schematic DSPWA. The CP interface uses page addressing to
save I/O pins. F0, F1 and F2 make up the page register. In addition there are the 2 address bits,
LA0 and LA1. A write to address 0 selects the page register with DSI[2:0] going to the page register
and selecting the page for the successive transfers. A read from address 0 reads the status register on
all pages. Pages 4 and 6 are the only ones implemented in this device. L1 latches the r/w level. The
write decoding generates DSIW which enables writes to the DFME8 registers reg1 and reg2 shown
on the HOST INTERFACE schematic. DSIW also clears the CP interrupt and restores HRDY.
DSWST writes to the host status register also shown on the HOST INTERFACE schematic.
DSWDREG implements writing to the data registers shown on IOPIL8 5 and DATREG. Finally
the logic at the bottom of the page generates CPCYC, a 1-clock interval after the CP cycle is over
that implements the actual writes to the registers. The use of the data bus latches and the post bus
cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices,
without requiring clocking at several times the bus speed.
DSPRA
The CP read control is contained on schematic DSPRA. The 2 by 16 bit mux selects CP status if the
CP latched address is 0 and IQ[15:0] if the address is not 0. The only significant status bits are bits 15
(indicating the CP is interrupting the host), bit 14 (1 indicating an 8-bit host interface) and bit 0 (set
to 1 during a host command transfer and 0 during data transfer).
HOST INTERFACE
Both the CP and the host use a special mode to transfer data to avoid unnecessary CP interrupts.
This special mode is under the control of the CP and is transparent to the host. When the CP
receives a command from the host it initializes the transfer by setting the number of transfers
expected (0,1,2 or 3) in the 2 LSB's of the host status register, REG3 and REG4 on HOST
INTERFACE. This write (DSWST) also loads these bits into the 2 bit down counter DCNT2 on
IOPIL8 5. Note that a Q8 low, which indicates a host command, asynchronously clears this register
enabling interrupts on schematic HICTLA. If DPNT[1:0] is not 0 and Q8 is high, indicating a host
data transfer, and SINT goes high indicating the end of a host cycle the counter is decremented.
MXAD2 selects address RA from the CP latched address bits if the page register contains 6, or the
counter contents DPNT[1:0] if not. This allows the CP to have direct access to registers 1, 2, and 3,
using address 1,2,and 3 on page 6. The host on the other hand can only read or write to the data
register, HA0 low and the counter will auto decrement from 3 down to 0 allowing the host to access
the registers on DATAREG where REG1=R1 and R2, REG2=R3 and R4, and REG3=R5 and R6.
The writes are enabled by the two decoders DECE2X4 while the reads are selected by the two 4x8
muxes, MUX1 and MUX2 controlled by the two 2x1 muxes MDS1 and MDS0. The output data
IQ[15:0] goes to HOST INTERFACE schematic below IOPIL8 1 and to DSPRA below IOPIL8 2.
The write data is HI[7:0] from the host and DSI[15:8] and DSI[7:0] from the CP. Note that END1
MC3510 Technical Specifications
47