MC3510 Datasheet, PDF (29/75 Pages) List of Unclassifed Manufacturers – Pilot Motion Processor

6 Parallel Communication
With the addition of an external logic device, the Pilot motion processor can communicate with a
host processor using a parallel data stream. This offers a higher communication rate than a serial
interface and may be used in configurations where a serial connection is not available or not
convenient. This section details the required logic that must be implemented in the external device
as well as the necessary connections to the CP chip.
The reference design files for the parallel interface chip, in Actel/ViewLogic format, are available
from PMD. There are two versions of the design, one for interfacing with host processors that have
an 8-bit data bus and one for host processors that have a 16-bit data bus. The designs are called
IOPIL8 and IOPIL16 respectively. The interface to the CP chip is essentially identical in both.
The function of the I/O chip is to provide a shared-memory style interface between the host and CP
chip, comprised of four 16-bit wide locations. These are used for transferring commands and data
between the host and Pilot motion processor. The CP chip accesses the command/data registers
using its 16-bit external data bus while the host accesses the registers via a parallel interface with chip
select, read, write and command/data signals. If necessary, the host side interface can be modified
by the designer to match specific requirements of the host processor.
6.1 Host interface pin description table
Pin Name
HostCmd
Direction
input
HostRdy
output
~HostRead
~HostWrite
~HostSlct
CPIntrpt
input
input
input
output
CPR/~W
CPStrobe
input
input
Description
This signal is asserted high to write a host instruction to the motion processor, or to
read the status of the HostRdy and HostIntrpt signals. It is asserted low to read or write
a data word.
This signal is used to synchronize communication between the motion processor
and the host. HostRdy will go low (indicating host port busy) at the end of a read or
write operation according to the interface mode in use, as follows:
Interface Mode HostRdy goes low
8/16
after the second byte of the instruction word
after the second byte of each data word is transferred
16/16
after the 16-bit instruction word
after each 16-bit data word
serial
n/a
HostRdy will go high, indicating that the host port is ready to transmit, when the last
transmission has been processed. All host port communications must be made
with HostRdy high (ready).
A typical busy-to-ready cycle is 12.5 microseconds, but can be substantially longer,
up to 100 microseconds.
When ~HostRead is low, a data word is read from the motion processor.
When ~HostWrite is low, a data word is written to the motion processor.
When ~HostSlct is low, the host port is selected for reading or writing operations.
I/O chip to CP chip interrupt. This signal sends an interrupt to the CP chip
whenever a host–chipset transmission occurs. It should be connected to CP chip
pin 53, I/OIntrpt.
This signal is high when the I/O chip is reading data from the I/O chip, and low
when it is writing data. It should be connected to CP chip pin 4, R/W.
This signal goes low when the data and address become valid during Motion
processor communication with peripheral devices on the data bus, such as external
memory or a DAC. It should be connected to CP chip pin 6, Strobe.
MC3510 Technical Specifications
29