MC3510 Datasheet, PDF (46/75 Pages) List of Unclassifed Manufacturers – Pilot Motion Processor

host. HA0 acts as an address bit, and usually is an address bit on the bus. When the host is writing,
HA0 low indicates data and HA0 high indicates a command. When the host is reading, HAO low
indicates data and HA0 high indicates status. Read status is the only transaction allowed while
HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two flops latch the
incoming data in the interface latches by driving ~HG1 low from the start of the write transaction
until the first negative clock transition after the first positive transition following the start of the write
cycle. This tail-biting circuit removes the requirement for hold time on the data bus.
HICTLA
Most of the control logic for the host interface is shown on schematic HICTLA. The sequencer at
the top generates HCYC one clock interval after the interface has been accessed and the host has
finished the transaction. The nature of the transaction, rd/wr, command/data, and read status is
preserved in the three flops F13, F8, and F9. Since 16 bit transfers must take place over an 8 bit bus
two transfers are required. The toggle flop is used to determine whether a cycle is the first or second
of the 2 required. The toggle flop may be initialized to the 0 state, which indicates that this is the
first transfer (high byte), by the CP writing a one to host status bit 15. This status bit is read by the
host as the HRDY bit and is not writable by the CP. In addition flop F12 and the associated gating
determine if the present command transaction is the first or second byte of a command. If the
toggle flop gets into the wrong state due to a missed or aborted transfer the next command will set it
back to the correct state. A host write or a CP write, DSIW, enable REG1 and REG2 on the HOST
INTERFACE schematic discussed previously. A host data write generates ~ENHD1 and
~ENHD2 for the data registers on the DATAREG schematic. For host writes ~EN2, ~EN1,
~ENHD2, and ~ENHD1 are also determined by the state of the toggle flop using HIEN and
LOEN. 1CMD is used in this logic to ensure correct behavior when the command is correcting the
state of the toggle. The logic at the bottom of the page generates the CP interrupt, the HRDY and
the HCMDFL. The HCMDFL is used in the CP status to indicate a command. DSIW, the CP
writing to REG1 and REG2 on the HOST INTERFACE schematic clears the interrupt and reasserts
HRDY. HRDY is de-asserted during all host transactions except read status, and stays de-asserted
until the CP has completed the DSIW cycle that clears the interrupt and reasserts HRDY. As
mentioned previously data transfers to and from the host use the data registers and do not interrupt
the CP. The CP knows the number of data transfers that must take place after decoding the
command. It places this number, 0-3, in the 2 least significant bits of the host status register,
HST[1:0]. These become DPNT[1:0] on this page of the schematic and enable an interrupt at 0 for a
read and 1 or 0 for a write. The CP always leaves these bits at 0 unless setting up a multiple word
data transfer. If INTEN is true and LRDST, latched read status, is false, HCYC will generate an
interrupt to the CP. This will also hold HRDY false until after the CP writes to the interface register,
DSIW, thereby generating ~CLRFLGS.
IOPIL8 4
The CP interface is shown in sheet IOPIL8 4. The incoming data DSD[15:0] is latched in the
transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from
the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL8 1 and
IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and
DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output
latches, which present the data during a CP read, are always transparent because GOUT is connected
to VDD. The latched I/O in the Actel part contains both input and output latches. The output
latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature.
The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal
is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input.
MC3510 Technical Specifications
46