CH1005C Datasheet, PDF (44/49 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder with Macrovision

CHRONTEL
CH7005C
Register Descriptions (continued)
Symbol:
Address: 1BH
Bits: 8
Bit:
7
6
5
4
3
2
1
0
Symbol:
P-OUTP FSCI19
FSCI18
FSCI17
FSCI16
Type:
R/W
R/W
R/W
R/W
R/W
Default:
0
0
0
0
0
Note: P-OUTP (bit 4) is used to invert the P-OUT signal.
Symbol:
Address: 1CH
Bits: 6
Bit:
7
6
5
4
3
2
1
0
Symbol:
DSEN
FSCI15
FSCI14
FSCI13
FSCI12
Type:
R/W
R/W
R/W
R/W
R/W
Default:
1
0
0
0
0
Note: DSEN (bit4) controls the BCO / Data Start I/O pin. When this bit is low, the pin continues to operate as the BCO
pin described in the BCO register description. When this bit is high, the pin becomes an input for the Data Start signal.
PLL Control Register
Bit:
7
6
Symbol:
Type:
Default:
5
PLLCPI
R/W
0
4
PLLCAP
R/W
0
3
PLLS
R/W
1
Symbol: PLLC
Address: 20H
Bits: 6
2
PLL5VD
R/W
0
1
PLL5VA
R/W
1
0
MEM5V
R/W
0
The following PLL and memory controls are available through the PLL control register:
MEM5V
MEM5V is set to 1 when the memory supply is 5 volts. The default value of 0 is used when the
memory supply is 3.3 volts.
PLL5VA
PLL5VA is set to 1 when the phase-locked loop analog supply is 5 volts (default). A value of 0 is
used when the phase-locked loop analog supply is 3.3 volts.
PLL5VD
PLL5VD is set to 1 when the phase-locked loop digital supply is 5 volts. A value of 0 is used when
the phase-locked loop digital supply is 3.3 volts (default).
PLLS
PLLS controls the number of stages used in the PLL. When the PLL5VA is 1 (5V analog PLL
supply) PLLS should be 1, and seven stages are used. When PLL5VA is 0 (3.3V analog PLL
supply) PLLS should be 0, and five stages are used.
PLLCAP
PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs.
Mode is shown below
PLLCPI
PLLCHI controls the charge pump current of the PLL. The default value should be used.
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201-0000-025 Rev 2.1, 8/2/99