CH1005C Datasheet, PDF (42/49 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder with Macrovision

CHRONTEL
Register Descriptions (continued)
CH7005C
Table 25. Clock Output Selection
SCO[2:0]
000
001
010
011
100
101
110
111
Buffered Clock Output
14MHz crystal
(for test use only)
VCO divided by K3 (see Table 26)
Field ID signal
(for test use only)
(for test use only)
TV horizontal sync (for test use only)
TV vertical sync (for test use only)
Table 26. K3 Selection
SHF[2:0]
K3
000
2.5
010
3.5
011
4
100
4.5
101
5
110
6
111
7
Subcarrier Value Registers
Symbol: FSCI
Address: 18H - 1FH
Bits: 4 or 8 each
Bit:
7
6
5
4
3
2
1
0
Symbol:
FSCI#
FSCI#
FSCI#
FSCI#
Type:
R/W
R/W
R/W
R/W
Default:
The lower four bits of registers 18H through 1FH contain a 32-bit value which is used as an increment value for the
ROM address generation circuitry. The bit locations are specified as the following:
Register
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Contents
FSCI[31:28]
FSCI[27:24]
FSCI[23:20]
FSCI[19:16]
FSCI[15:12]
FSCI[11:8]
FSCI[7:4]
FSCI[3:0]
42
201-0000-025 Rev 2.1, 8/2/99