CH1005C Datasheet, PDF (38/49 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder with Macrovision

CHRONTEL
CH7005C
Register Descriptions (continued)
Power Management Register
Symbol: PMR
Address: 0EH
Bits: 5
Bit:
7
6
5
4
3
2
1
0
Symbol:
SCART
Reset*
PD2
PD1
PD0
Type:
R/W
R/W
R/W
R/W
R/W
Default:
0
1
0
1
1
This register provides control of the power management functions, a software reset (ResetB), and the SCART output
enable. The CH7005 provides programmable control of its operating states, as described in the table below.
Table 22. Power Management
PD[2:0]
000
001
Operating State
Composite Off
Power Down
010
S-Video Off
011
Normal (On)
1XX
Full Power Down
Functional Description
CVBS DAC is powered down
Most pins and circuitry are disabled (except for the buffered clock outputs
which are limited to the 14MHz output and VCO divided output when the
DS/BCO pin is selected to be an output).
S-Video DACs are powered down
All circuits and pins are active.
All circuitry is powered down, except I²C circuit.
Reset* (bit 3) is soft reset. Setting this bit to 0 will reset all circuitry requiring a power on reset, except for this bit
itself and the I²C state machines. After reset, this bit should be set back to 1 for normal operation to continue.
SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7005 will operate normally, outputting Y/C
and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from
the DACs and composite sync from the CSYNC pin.
Note: For complete details regarding the operation of these modes, see the Power Management in Functional Description
sections.
Connection Detect Register
Symbol: CDR
Address: 10H
Bits: 4
Bit:
7
6
5
4
3
2
1
0
Symbol:
YT
CT
CVBST
SENSE
Type:
R
R
R
W
Default:
0
0
0
0
The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or Composite
video outputs. The status bits, YT, CT, and CVBST correspond to the DAC outputs for S-Video (Y and C outputs)
and Composite video (CVBS), respectively. However, the values contained in these status bits are NOT VALID
until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of
outputs, then reading out the applicable status bits. The detection sequence works as follows:
1. Ensure the power management register Bits 2-0 is set to 011(normal mode).
38
201-0000-025 Rev 2.1, 8/2/99