CH1005C Datasheet, PDF (1/49 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder with Macrovision

CH7005C
CHRONTEL
Digital PC to TV Encoder with Macrovision^TM
Features
• Supports Macrovision^TM 7.X anti-copy protection
• Function compatible with CH7004
• Universal digital interface accepts YCrCb (CCIR601
or 656) or RGB (15,16 or 24-bit) video data in both
non-interlaced and interlaced formats
• TrueScale ^TM rendering engine supports undescam
operations for various graphic resolutions† ¥
• Enhanced text sharpness and adaptive flicker removal
with up to 5-lines of filtering†
• Enhanced dot crawl control and area reduction
• Fully programmable through I²C port
• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,
G, H, I, M and N) TV formats
• Provides Composite, S-Video and SCART outputs
• Auto-detection of TV presence
• Supports VBI pass-through
• Programmable power management
• 9-bit video DAC outputs
• Complete Windows and DOS driver software
• Offered in 44-pin PLCC, 44-pin TQFP
† Patent number 5,781,241
Â¥ Patent number 5,914,753
General Description
Chrontel’s CH7005 digital PC to TV encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output. Suggested application use with the
Intel I740.* It provides a universal digital input port to
accept a pixel data stream from a compatible VGA
controller (or equivalent) and converts this directly into
NTSC or PAL TV format.
This circuit integrates a digital NTSC/PAL encoder with
9-bit DAC interface, and new adaptive flicker filter, and
high accuracy low-jitter phase locked loop to create
outstanding quality video. Through its TrueScale^TM
scaling and deflickering engine, the CH7005 supports full
vertical and horizontal underscan capability and operates
in 5 different resolutions including 640x480 and 800x600.
A new universal digital interface along with full
programmability make the CH7005 ideal for system-level
PC solutions. All features are software programmable
through a standard I²C port, to enable a complete PC
solution using a TV as the primary display.
LINE
MEMORY
D[15:0]
PIXEL DATA
DIGITAL
INPUT
INTERFACE
RGB-YUV
CONVERTER
TRUE SCALE
SCALING &
DEFLICKERING
ENGINE
YUV-RGB CONVERTER
NTSC/PAL
ENCODER
& FILTERS
TRIPLE
DAC
I²C REGISTER &
CONTROL BLOCK
SYSTEM CLOCK
PLL
TIMING & SYNC
GENERATOR
SC SD
201-0000-025 Rev 2.1, 8/2/99
RESET*
XCLK
H
V XI XO/FIN CSYNC P-OUT DS/BCO
Figure 1: Functional Block Diagram
*Intel I740 is a Trademark of Intel Corp
Y/R
C/G
CVBS/B
RSET
1