CH1005C Datasheet, PDF (33/49 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder with Macrovision

CHRONTEL
CH7005C
Register Descriptions (continued)
Video Bandwidth Register
Bit:
Symbol:
Type:
Default:
7
FLFF
R/W
0
6
CVBW
R/W
0
5
CBW1
R/W
0
4
CBW0
R/W
0
3
YPEAK
R/W
0
2
YSV1
R/W
0
Symbol: VBW
Address: 03H
Bits: 7
1
YSV0
R/W
0
0
YCV
R/W
0
This register enables the selection of alternative filters for use in the luma and chroma channels. There are currently
four filter options defined for the chroma channel, 4 filter options in the S-Video luma channel and two filter options
in the composite luma channel. The Table 18 and 19 below show the various settings.
Table 18. Luma Filter Bandwidth
YCV
0
1
YSV[1:0]
00
01
10
11
YPEAK
0
1
Luma Composite Video Filter Adjust
Low bandwidth
High bandwidth
Luma S-Video Filter Adjust
Low bandwidth
Medium bandwidth
High bandwidth
Reserved (decode this and handle the same as 10)
Disables the Y-peaking circuit
Disables the peaking filter in luma S-Video channel
Enables the peaking filter in luma S-Video channel
Table 19. Chroma Filter Bandwidth
CBW[1:0]
00
01
10
11
Chroma Filter Adjust
Low bandwidth
Medium bandwidth
Med-high bandwidth
High bandwidth
Bit 6 (CVBW) outputs the S-Video luma signal on both the S-Video luma output and the CVBS output. A "1" in this
location enables the output of a black and white image on composite, thereby eliminating the degrading effects of
the color signal (such as dot crawl or false colors), which is useful for viewing text with high accuracy.
Bit 7 (FLFF) controls the flicker filter used in the 7/10’s scaling modes. In these scaling modes, setting FLFF to 1
causes a five line flicker filter to be used. The default setting of 0 uses a four line flicker filter.
201-0000-025 Rev 2.1, 8/2/99
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