CH1005C Datasheet, PDF (29/49 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder with Macrovision

CHRONTEL
CH7005C
Registers and Programming
The CH7005 is a fully programmable device, providing for full functional control through a set of registers accessed
from the I²C port. The CH7005 contains a total of 37 registers, which are listed in Table 14 and described in detail
under Register Descriptions. Detailed descriptions of operating modes and their effects are contained in the previ-
ous section, Functional Description. An addition (+) sign in the Bits column below signifies that the parameter con-
tains more than 8 bits, and the remaining bits are located in another register.
Table 14. Register Map
Register
Display Mode
Flicker Filter
Video Bandwidth
Input Data Format
Clock Mode
Start Active Video
Position Overflow
Black Level
Horizontal Position
Vertical Position
Symbol
DMR
FFR
VBW
IDF
CM
SAV
PO
BLR
HPR
VPR
Sync Polarity
Power Management
Connection Detect
Contrast Enhancement
PLL M and N extra bits
PLL-M Value
PLL-N Value
Buffered Clock
Subcarrier Frequency
Adjust
PLL and Memory Control
CIV Control
Calculated Fsc Increment
Value
Version ID
Test
SPR
PMR
CDR
CE
MNE
PLLM
PLLN
BCO
FSCI
PLLC
CIVC
CIV
VID
TR
Address
AR
Address
00H
01H
03H
04H
06H
07H
08H
09H
0AH
0BH
0DH
0EH
10H
11H
13H
14H
15H
17H
18H -1FH
20H
21H
22H -
24H
25H
26H -
29H
3FH
Bits
8
6
7
7
8
8+
3
8
8+
8+
4
5
4
3
5
8+
8+
6
4 or 8
each
6
5
8 each
8
30
6
Functional Summary
Display mode selection
Flicker filter mode selection
Luma and chroma filter bandwidth selection
Data format and bit-width selections
Sets the clock mode to be used
Active video delay setting
MSB bits of position values
Black level adjustment input latch clock edge select
Enables horizontal movement of displayed image on
TV
Enables vertical movement of displayed image on
TV
Determines the horizontal and vertical sync polarity
Enables power saving modes
Detection of TV presence
Contrast enhancement setting
Contains the MSB bits for the M and N PLL values
Sets the PLL M value - bits (7:0)
Sets the PLL N value - bits (7:0)
Determines the clock output at pin 41
Determines the subcarrier frequency
Controls for the PLL and memory sections
Control of CIV value
Readable register containing the calculated
subcarrier increment value
Device version number
Reserved for test (details not included herein)
Current register being addressed
201-0000-025 Rev 2.1, 8/2/99
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