82C862 Datasheet, PDF (43/51 Pages) List of Unclassifed Manufacturers – FireLink USB Dual Controller Quad Port USB

FireLink USB
82C862
5.2.2 Legacy Support Registers
Four registers are provided for legacy support:
1. HceControl
- - Used to enable and control the emulation hardware and report various status information.
2. HceInput
- - Emulation side of the legacy Input Buffer register.
3. HceOutput
- - Emulation side of the legacy Output Buffer register where keyboard and mouse data is to be written by software.
4. HceStatus
- - Emulation side of the legacy Status register.
These registers are located in the Host Controller Register Space; from MEMOFST 100h through 10Fh. The bit formats for
these registers are described in Table 5-3.
Refer to "Legacy Support" section for information when accessing these registers when emulation is enabled.
5.2.3 MEMOFST 100h-1Fh (Legacy Support Registers)
7
6
5
4
3
2
1
0
MEMOFST 100h
HceControl Register - Byte 0
Default = 00h
IRQ12 Active IRQ1 Active
GateA20
External
Indicates that a Indicates that a
Sequence
IRQEn
positive
positive
Set by HC
IRQ1 and
transition of
transition of
when a data IRQ12 from
IRQ12 from
IRQ1 from
value of D1h is kybrd controller
kybrd controller kybrd controller written to Port causes
has occurred. has occurred. 64h.
emulation
Writing a 1
Writing a 1
Cleared by HC ^interrupt:
clears this bit, clears this bit, on write to Port 0 = Disable
while writing a 0 while writing a 0 64h of any
1 = Enable
leaves it
unchanged.
leaves it
unchanged.
value other than
D1h.
This bit is
independent of
the Emulation
Enable bit (bit
0) setting.
IRQEn
Character
If the Output
Pending
Full bit
HC generates
(MEMOFST emulation
10Ch[0]) = 1, interrupt when
HC generates the Output Full
IRQ1 or IRQ12. bit (MEMOFST
If the Aux
10Ch[0]) = 0.
Output Full bit 0 = Disable
(MEMOFST 1 = Enable
10Ch[5]) = 0,
HC generates
IRQ1; if = 1, HC
generates
IRQ12.
0 = Disable
1 = Enable
Emulation
Interrupt (RO)
Emulation
Enable
A static decode HC is enabled
of the emulation for legacy
interrupt
emulation?
condition.
0 = No
1 = Yes(1)
(1) The HC decodes accesses to Ports 60h/64h and generates IRQ1 and/or IRQ12 when appropriate. Additionally, the HC generates an
emulation interrupt at appropriate times to invoke the emulation software.
MEMOFST 101h
HceControl Register - Byte 1
Reserved
Default = 00h
A20 State:
Indicates
current state of
Gate A20 on
kybrd controller.
Used to
compare
against value
written to Port
60h when
GateA20
Sequence is
active.
MEMOFST 102h-103h
HceControl Register - Bytes 2 & 3
Default = 00h
912-2000-030
Revision 1.0
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