82C862 Datasheet, PDF (12/51 Pages) List of Unclassifed Manufacturers – FireLink USB Dual Controller Quad Port USB

FireLink USB
82C862
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#
CLKRUN#
GPIO2
69
I/O Device Select: The 82C862 claims a PCI cycle via positive decoding by
(s/t/s) asserting DEVSEL#. As an output, the 82C862 drives DEVSEL# for two different
reasons:
1. If the 82C862 samples IDSEL active in configuration cycles, DEVSEL# is
asserted.
2. When the 82C862 decodes an internal address or when it subtractively
decodes a cycle, DEVSEL# is asserted
When DEVSEL# is an input, it indicates the target response to an 82C862
master-initiated cycle. DEVSEL# is tristated from the leading edge of RESET#
and remains so until driven by the 82C862 acting as a slave.
50
I
Initialization Device Select: This signal is the "chip select" during configuration
read and write cycles. IDSEL is sampled by the 82C862 during the address
phase of a cycle. If IDSEL is found to be active and the bus command is a
configuration read or write, the 82C862 claims the cycle with DEVSEL#.
71
I/O Parity Error: The 82C862 uses this line to report data parity errors during any
PCI cycle except a Special Cycle.
75
I
System Error: The 82C862 uses this line to report address parity errors and data
parity errors on the Special Cycle command, or any other system error where the
result will be catastrophic.
36
O
Bus Request: REQ# is asserted by the 82C862 to request ownership of the PCI
bus.
35
I
Bus Grant: GNT# is sampled by the 82C862 for an active low assertion, which
indicates that it has been granted use of the PCI bus.
46
I/O Clock Run: The CLKRUN# function is available on this pin and can be used to
reduce chip power consumption during idle periods. It is an I/O sustained tristate
signal and follows the PCI 2.1 defined protocol.
General Purpose I/O pin 2: These pins can be written or read by specific
application software. Refer to PCICFG 53-55h for information.
3.3.3 USB Interface Signals
Signal Name
Pin
Pin
No.
Type
D1+/D1-
D2+/D2-
D3+/D3-
D4+/D4-
PWRON1#
PWRON2#
PWRON3#
PWRON4#
PWRFLT1#
PWRFLT2#
PWRFLT3#
PWRFLT4#
13/14
diff
15/16
diff
28/29
diff
30/31
diff
53
O
24
73
90
54
I
23
74
91
Signal Description
USB Port 1 Differential Data Pair: This pair comes from the first controller.
USB Port 2 Differential Data Pair: This pair comes from the first controller.
USB Port 3 Differential Data Pair: This pair comes from the second controller.
USB Port 4 Differential Data Pair: This pair comes from the second controller.
Power On Lines 1, 2, 3 and 4: These outputs are used to switch port VCC for
the respective USB port. The controlled VCC is used only by the device
connected to the port, and is not used by the 82C862 controller.
Power Fault Lines 1, 2, 3 and 4: These inputs indicate that an over-current fault
has occurred on the respective USB port. Their polarity can be both strap- and
software-controlled: Refer to the Strap Options section for details.
®
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912-2000-030
Revision: 1.0