82C862 Datasheet, PDF (10/51 Pages) List of Unclassifed Manufacturers – FireLink USB Dual Controller Quad Port USB

FireLink USB
82C862
3.3 Signal Descriptions
3.3.1 Clock and Reset Interface Signals
Signal Name
Pin
Pin Signal Description
No.
Type
PCICLK
X1/CLK48
X2
RESET#
34
I
PCI Clock: This input provides timing for all cycles on the host PCI bus; normally
33MHz. All other PCI signals are sampled on the rising edge of PCLK (timing
parameters refer to this edge).
6
I
USB Clock: The CLK48 input provides timing for USB data signals; this clock
8
O
must be 48MHz for proper USB operation. As an option, a 12MHz crystal can be
connected across X1 and X2, in which case an internal PLL will develop the
48MHz signal. Refer to the TEST0-TEST1 strap options for selecting the mode of
operation.
19
O
Reset: If RESET# is asserted for a minimum of 1µs while PCICLK is stable at
33MHz, it causes the 82C862 to enter its default state (all registers are set to
their default values).
AD[31:0], C/BE[3:0]#, and PAR are always driven low by the 82C862
synchronously from the leading edge of RESET# and are always tristated from
the trailing edge of RESET#. FRAME#, IRDY#, TRDY#, STOP#, and DEVSEL#
are tristated from the leading edge of RESET# and remain so until driven as
either a master or slave by the 82C862. RESET# may be asynchronous to
PCICLK when asserted or negated, however, negation must occur with a clean,
bounce-free edge.
3.3.2 PCI Bus Interface Signals
Signal Name
Pin
No.
Pin Signal Description
Type
AD[31:0]
C/BE[3:0]#
37:39,
42:45,
49, 51,
55:58,
61:62,
78:79,
82:84,
86:88,
93:95,
99:100,
2:1
49, 63,
77, 89
I/O Address and Data Lines 31 through 0: This bus carries the address and/or
data during a PCI bus cycle. A PCI bus cycle has two phases - an address phase
which is followed by one or more data phases. During the initial clock of the bus
cycle, the AD bus contains a 32-bit physical byte address. AD[7:0] is the least
significant byte (LSB) and AD[31:24] is the most significant byte (MBS). After the
first clock of the cycle, the AD bus contains data.
When the 82C862 is the target, AD[31:0] are inputs during the address phase.
For the data phase(s) that follow, the 82C862 may supply data on AD[31:0] in the
case of a read or accept data in the case of a write.
When the 82C862 is the master, it drives a valid address on AD[31:2] during the
address phase, and drives write or accepts read data on AD[31:0] during the data
phase. As a master, the 82C862 always drives AD[1:0] low.
I/O Bus Command and Byte Enables 3 through 0: These signals provide the
command type information during the address phase and carry the byte enable
information during the data phase. C/BE0# corresponds to byte 0, C/BE1# to byte
1, C/BE2# to byte 2, and C/BE3# to byte 3. If the 82C862 is the initiator of a PCI
bus cycle, it drives C/BE[3:0]#. When it is the target, it samples C/BE[3:0]#.
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Revision: 1.0