82C862 Datasheet, PDF (24/51 Pages) List of Unclassifed Manufacturers – FireLink USB Dual Controller Quad Port USB

FireLink USB
82C862
4.5.1 Legacy Support
Four registers are provided for legacy support:
1. HceControl
- - Used to enable and control the emulation hardware and report various status information.
2. HceInput
- - Emulation side of the legacy Input Buffer register.
3. HceOutput
- - Emulation side of the legacy Output Buffer register where keyboard and mouse data is to be written by software.
4. HceStatus
- - Emulation side of the legacy Status register.
These registers are located in the Host Controller Register Space; from MEMOFST 100h through 10Fh. Table 4-3 shows a
register map of these registers. Refer to Section 5.2.2, "Legacy Support Registers" for detailed bit information.
Table 5. Legacy Support Register Map
MEMOFST
R/W Register Name
100h-103h
104h-107h
108h-10Bh
10Ch-10Fh
R/W HceControl
R/W HceInput
R/W HceOutput
R/W HceStatus
4.5.2 Intercept Port 60h and 64h Accesses
The HceStatus, HceInput, and HceOutput registers are accessible at I/O Ports 60h and 64h when emulation is enabled. Reads
and writes to these registers using the I/O Ports do have some side effects as shown in Table 4-4. However, accessing these
registers directly through their memory address produces no side effects.
When emulation is enabled, I/O accesses of Ports 60h and 64h must be handled by the Host Controller (HC). The HC must be
positioned in the system so that it can do a positive decode of accesses to Ports 60h and 64h on the PCI bus. If a keyboard
controller is present in the system, it must either use subtractive decode or have provisions to disable its decode of Ports 60h
and 64h. If the legacy keyboard controller uses positive decode and is turned off during emulation, it must be possible for the
emulation code to quickly re-enable and disable the legacy keyboard controller Port 60h and 64h decode. This is necessary to
support a mixed operating environment.
Table 6. Emulated Registers and Side Effects
Register Contents Side Effect
Accessed/Modified
HceOutput
HceInput
• A read from Port 60h will set the Output Full bit (MEMOFST 10Ch[0]) to 0.
• A write to Port 60h will set the Input Full bit (MEMOFST 10Ch[1]) to 1 and the Cmd Data bit
(MEMOFST 10Ch[3]) to 0.
HceStatus
• A write to Port 64h will set the: Input Full bit (MEMOFST 10Ch[1]) to 0 and the Cmd Data bit
(MEMOFST 10Ch[3]) to 1.
• A read from Port 64h returns the current value of the HceStatus register.
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Revision: 1.0