82C862 Datasheet, PDF (19/51 Pages) List of Unclassifed Manufacturers – FireLink USB Dual Controller Quad Port USB

FireLink USB
82C862
4.3 Clock Generation
The USB core requires an accurate 48MHz internal clock for proper operation. This clock can be obtained either by connecting
an external 48MHz oscillator, or by connecting a 12MHz crystal.
To use the external 48MHz clock, connect the clock source to the X1 pin and strap TEST1 high. The X2 pin is not used in this
configuration and must be left floating. This clock must be accurate to +/- 0.2%, or 2000ppm.
To use a 12MHz crystal, connect it to the X1 and X2 pins and strap TEST1 low. An internal PLL develops the required 48MHz
clock. This PLL can be powered down when not in use through the PCI Power Management registers. Since the 12MHz clock
generated is used to develop 48MHz internally, its accuracy must be within +/- 0.05%, or 500ppm.
4.4 Power Management Features
FireLink USB 82C862 implements new power management features which can reduce the overall power consumed in mobile
USB applications. Key features are as follows.
The OS can put each USB controller module individually into USBSuspend state.
Once in USBSuspend state, the BIOS can turn off the USB I/O cells on each port for further power savings.
The external PCI clock can be stopped if system hardware is designed to use the CLKRUN# pin from the 82C862 chip, which
can also be used to awaken the system.
The external 48MHz USB clock can also be stopped along with the PCICLK when the system will be put into a Standby mode.
USB clocks to each of the internal modules can be stopped independently through the PCI power management registers.
Each of these features is described in the sections below.
4.4.1 Putting FireLink into USBSuspend State
Before a host system goes into a suspend state, the operating system should put the OHCI USB controller into USBSuspend
mode by writing to register MEMOFST 04h[7:6] = 11.
4.4.2 Powering Down the USB I/O Cells
Once in USBSuspend state, the USB I/O cells can be disabled to reduce power by setting PCICFG 50h[1:0] = 11. If this
feature is used, the I/O cells should be disabled by the BIOS before going into system-level Suspend, and re-enabled by the
BIOS before giving control back to the operating system.
4.4.3 Stopping the 48MHz USB Clock
After the controller is put into USBSuspend state, still another step can be taken to further reduce power consumption: stop the
48MHz USB clock. If this route is taken, the USB clock must be stopped and started in a glitch free manner. The usual means
of effecting this control would be through software control of the system clock generator circuit.
Once the USB clock is stopped, the system can be awakened by using PME#, which will be asserted on a USB wake up event
(resume signalling, connect, disconnect). This system event should be designed to restart the 48MHz clock to the USB
controller.
4.4.4 Using CLKRUN#
The CLKRUN# pin is always operational in the 82C862 part; no enabling is required. The PCI Mobile Design Guide, available
from the PCISIG, describes the operation of CLKRUN# in detail. Briefly, connected devices monitor this pin to see if it goes
high, indicating that the host wants to stop the system PCICLKs. If the line goes high, connected devices are allowed to
momentarily drive the pin low. The host will then take over driving this pin low until it wants to try again to stop the clocks.
The host system uses CLKRUN# to determine whether or not the 82C862 USB controller requires a PCI clock by releasing
CLKRUN#, which is always pulled high with a resistor. The USB controller power management logic will drive this pin low
again as required by the CLKRUN# specification if the controller is using the clock, i.e. whenever a USB device is attached. If
the controller does not drive the clock low, the system is free to slow or stop the PCI clock.
912-2000-030
Revision 1.0
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