82C862 Datasheet, PDF (29/51 Pages) List of Unclassifed Manufacturers – FireLink USB Dual Controller Quad Port USB

FireLink USB
82C862
7
6
5
4
3
2
1
0
PCICFG 07h
Status Register - Byte 1
Detected
parity error:
This bit is set to
1 whenever the
USB core
detects a parity
error, even if
PCICFG 04h[6]
is disabled.
Write 1 to clear.
SERR#
status:
This bit is set to
1 whenever the
USB core
detects a PCI
address parity
error.
Write 1 to clear.
Received
master abort
status:
Set to 1 when
the USB core,
acting as a PCI
master, aborts
a PCI bus
memory cycle.
Write 1 to clear.
Received
target abort
status:
This bit is set to
1 when a USB
core generated
PCI cycle (USB
core is the PCI
master) is
aborted by a
PCI target.
Signaled target
abort status:
This bit is set to
1 when the
USB core
signals target
abort.
Write 1 to clear.
DEVSEL timing (RO):
Indicates DEVSEL# timing when
performing a positive decode.
Since DEVSEL# is asserted to
meet the medium timing, these
bits are encoded as 01.
Write 1 to clear.
Default = 02h
Data parity
reported:
Set to 1 if
PCICFG 04h[6]
is set and the
USB core
detects PERR#
asserted while
acting as PCI
master
(whether
PERR# was
driven by USB
core or not.)
PCICFG 08h
Revision Identification Register (RO)
Default = 20h
PCICFG 09h
PCICFG 0Ah
PCICFG 0Bh
Class Code Register (RO)
Default = 10h
Default = 03h
Default = 0Ch
PCICFG 0Ch
Cache Line Size Register
Default = 00h
PCICFG 0Dh
Master Latency Timer Register
Default = 00h
PCICFG 0Eh
Header Type Register (RO)
Default = 00h
PCICFG 0Fh
Reserved
Default = 00h
PCICFG 10h-13h
Base Address Register 0
Default = 00h
This register identifies the base address of a contiguous memory space in main memory. POST will write all 1s to this register, then
read back the value to determine how big of a memory space is requested. After allocating the requested memory, POST will write the
upper bytes with the base address.
Bits [31:0] correspond to: 10h = [7:0], 11h = [15:8], 12h = [23:16], 13h = [31:24].
- Bit [0] - Indicates that the operational registers are mapped into memory space. Always = 0.
- Bits [2:1] - Indicates that the base register is 32 bits wide and can be placed anywhere in 32-bit memory space. Always = 0.
- Bit [3] - Indicates no support for prefetchable memory. Always = 0.
- Bits [11:4] - Indicates a 4K byte address range is requested, Always = 0.
- Bits [31:12] - Base Address: Post writes the value of the memory base address to this register.
PCICFG 14h-2Bh
Reserved
Default = 00h
PCICFG 2Ch
Subsystem Vendor ID Register (RO) - Byte 0
The Subsystem Vendor ID register is read-only but its value can be changed through PCICFG 7Dh:7Ch.
PCICFG 2Dh
Subsystem Vendor ID Register (RO) - Byte 1
Default = 45h
Default = 10h
PCICFG 2Eh
Subsystem ID Register (RO) Byte 0
The Subsystem ID register is read-only but its value can be changed through PCICFG 7Fh:7Eh.
PCICFG 2Fh
Subsystem ID Register (RO) Byte 1
Default = 61h
Default = C8h
PCICFG 30h-33h
Reserved
Default = 00h
912-2000-030
Revision 1.0
®
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