82C862 Datasheet, PDF (13/51 Pages) List of Unclassifed Manufacturers – FireLink USB Dual Controller Quad Port USB

FireLink USB
82C862
3.3.4 Host Controller shared signals: PME#, SMI#, REQ#, GNT#
Several other signals are shared by both host controllers in addition to the bused PCI signals. The shared signals are all active
low. The diagram below best explains the internal connections of the 82C862 device.
FireLink USB
USB
Host1
GNT1#
REQ1#
SMI1#
PME1#
USB
Host2
GNT2#
REQ2#
SMI2#
PME2#
Internal
Arbiter
GNT#
REQ#
SMI#
PME#
3.3.5 Legacy and Interrupt Interface Signals
Signal Name
Pin
Pin Signal Description
No.
Type
SMI#
GPIO4
PME#
GPIO3
INTA#
TEST0
GPIO0
TEST1
GPIO1
97
O
System Management Interrupt: This signal is used to request a System
Management Mode (SMM) interrupt. It can be connected to a spare EPMI pin on
the host chipset.
General Purpose I/O pin 4: These pins can be written or read by specific
application software. Refer to PCICFG 53-55h for information.
72
special Power Management Event: This signal is used to wake up the system from a
PCI Power Management (PCI/PM) power saving mode. This pin is normally tri-
stated and is driven low when active.
Note: When unpowered, the PME# driver output circuit will not be damaged if
PME# is powered from another source. Moreover, once power is removed from
the chip, this pin does not present a current path to ground.
General Purpose I/O pin 3: These pins can be written or read by specific
application software. Refer to PCICFG 53-55h for information.
1
O
PCI Interrupt A: This signal can be connected to a PCI interrupt line.
21
I/O TEST Pin 0: This pin is sampled by the chip at reset time to put the logic into a
test mode if needed. See the STRAP OPTIONS section for details.
General Purpose I/O pin 0: These pins can be written or read by specific
application software. Refer to PCICFG 53-55h for information.
25
I/O TEST Pin 1: This pin is sampled by the chip at reset time to put the logic into a
test mode if needed. See the STRAP OPTIONS section for details.
General Purpose I/O pin 1: These pins can be written or read by specific
application software. Refer to PCICFG 53-55h for information.
912-2000-030
Revision 1.0
®
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