W3100A Datasheet, PDF (38/63 Pages) List of Unclassifed Manufacturers – i2Chip W3100A

MACL_RAW starting point
MACL_RAW
C0_TW_PR = A
C0_TR_PR = A
MACL_RAW
sendto
cal FBS(free
buffer size)
FBS <=
C0_TW_PR -
C0_TR_PR
No
FBS >
SDS(send
data size)
Yes
Yes
Send bit == check previous
'1'
send comand
write data from
C0_TW_PR
No
write data
C0_TW_PR <=
C0_TW_PR + SDS
update
C0_TW_PR
send command
MACL_RAW Mode Data Reception Management
MACL_RAW Reception Memory Management
0x2000
0x2000
C0_RW_PR and
C0_RR_PR are
equal
(0x00000200
assumed)
0x0400
0x2000
C0_RW_PR is
increased to
0x00000400
(W3100A)
0x0580
0x0400
Rx
Data
head
0x2000
C0_RW_PR is
increased to
0x00000580
(W3100A)
0x0580
0x0400
Rx
Data
head
0x2000
C0_RW_PR
0x0580
C0_RW_PR
0x0200
Rx
Data
0x0200 ^head
Rx
Data
0x0200 ^head
0x0200
C0_RR_PR
C0_RR_PR
C0_RR_PR is
increased to
0x00000400
(MCU)
C0_RR_PR is
increased to
0x00000580
(MCU)
0x0000
0x0000
0x0000
0x0000
0x0000
Since reception
When C0_RW_PR is
When C0_RW_PR is
memory is 8KB, increased by receiving data increased by receiving data
mask is 0x00001FFF from the peer at W3100A from the peer at W3100A
When MCU completes
the processing of the
received data and
C0_RR_PR is increased
When MCU completes
the processing of the
received data and
C0_RR_PR is increased
MACL_RAW Mode’s Reception memory management uses 1 channel only, therefore all 8KB is allocated to
Channel 0. Above diagram illustrates the processing of 2 data after C0_WR_PR and C0_RR_PR are
equally initialized as 0x00000200.
MACL_RAW Mode Data Reception
In W3100A’s MACL_RAW Mode, the reception of the set packets are made according to the receive options
as set at C0_SOPR. As in UDP, header information is included in the received data in addition to the data,
and the header is structure as below.
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Z_