W3100A Datasheet, PDF (15/63 Pages) List of Unclassifed Manufacturers – i2Chip W3100A

7
6
5
4
3
2
1
0
C3R
C2R
C1R
C0R
C3
C2
C1
C0
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Symbol
C0
C1
C2
C3
C0R
C1R
C2R
C3R
Description
Occurrence of Channel 0 Socket Interrupt
Occurrence of Channel 1 Socket Interrupt
Occurrence of Channel 2 Socket Interrupt
Occurrence of Channel 3 Socket Interrupt
Occurrence of Channel 0 Socket data receipt
Occurrence of Channel 1 Socket data receipt
Occurrence of Channel 2 Socket data receipt
Occurrence of Channel 3 Socket data receipt
IMR (Interrupt Mask Register) [R/W, 0x09]
This register is used to mask an interrupt from each bit of the corresponding interrupt register. Interrupt is
enabled when the corresponding bit of the interrupt register is set by setting the corresponding bit at ‘1’.
7
IM_C3R
6
IM_C2R
5
IM_C1R
4
IM_C0R
3
IM_C3
2
IM_C2
1
IM_C1
0
IM_C0
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Symbol
IM_C0
IM_C1
IM_C2
IM_C3
IM_C0R
IM_C1R
IM_C2R
IM_C3R
Description
Channel 0 Socket Interrupt Enable.
Channel 1 Socket Interrupt Enable.
Channel 2 Socket Interrupt Enable.
Channel 3 Socket Interrupt Enable.
Channel 0 Socket data receipt Interrupt Enable.
Channel 1 Socket data receipt Interrupt Enable.
Channel 2 Socket data receipt Interrupt Enable.
Channel 3 Socket data receipt Interrupt Enable.
IDM_OR (InDirect Mode Option Register) [R/W, 0x0C]
This register facilitates indirect bus I/F mode enable and option set-up.
IND_EN (indirect mode enable) bit enables indirect bus I/F mode. H/W reset is required to convert from
indirect bus I/F mode to another I/F.
L/B (Little-endian/Big-endian) bit enables the access to indirect address register as Little-endian (‘1’) or Big-
endian (‘0’).
oˆ™‹ž™Œ‹Gp•›Œ™•Œ›Gj–••ŒŠ›› G~¡ˆ™‹GO~p•Œ›SGp•ŠUPG
X\