VS1001K Datasheet, PDF (34/40 Pages) List of Unclassifed Manufacturers – MPEG AUDIO CODEC

VLSI
Solution ^y
DATASHEET
VS1001K
8. WRITING SOFTWARE
Instruction (32−bit)
0000
0097
0780
07FF
1380
13FF
X (16−bit)
Stack
User
Space
Y (16−bit)
Stack
0000
0097
User
Space
0780
07FF
1380
13FF
4000
4020
43FF
System Vectors
User
Instruction
Space
Hardware
Registers
4000
4020
43FF
8000
8020
83FF
Instruction
Shadow
Memory
MSBs
Instruction
Shadow
Memory
8000
8020
LSBs
83FF
Figure 13: User’s Memory Map.
8.4.3 DAC Registers, 0x4200
DAC data should be written at each audio interrupt to DAC LEFT (0x4200) and DAC RIGHT (0x4201)
as signed values. INT FCTLL (0x4202) is not a user-serviceable register.
8.4.4 Interrupt Registers, 0x4300
INT ENABLE (0x4300) controls the interrupts. Bit 0 switches the DAC interrupt on (1) and off (0), bit 1
controls the SCI interrupt, and bit 2 controls the DATA interrupt. It may take upto 6 clock cycles before
changing this register has any effect.
By writing any value to INT GLOB DIS (0x4301) adds one to the interrupt counter and effectively
disables all interrupts. It may take upto 6 clock cycles before writing this register has any effect.
Writing any value to INT GLOB ENA (0x4302) subtracts one from the interrupt counter. If the interrupt
counter becomes zero, interrupts selected with INT ENABLE are restored. An interrupt routine should
always write to this register as the last thing it does, because interrupts automatically add one to the
interrupt counter, but subtracting it back to its initial value is on the responsibility of the user. It may take
upto 6 clock cycles before writing this register has any effect.
By reading INT COUNTER (0x4303) the user may check if the interrupt counter is correct or not. If the
register is not 0, interrupts are disabled. This register may not be written to.
Version 4.14, 2004-02-10
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