VS1001K Datasheet, PDF(17/40 Page) List of Unclassifed Manufacturers

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VS1001K Datasheet, PDF (17/40 Pages) List of Unclassifed Manufacturers – MPEG AUDIO CODEC

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VLSI

Solution y

DATASHEET

VS1001K

5. SPI BUSES

5 SPI Buses

5.1 General

The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1001kâs

Serial Data Interface SDI (Chapters 5.3 and 6.3) and Serial Control Interface SCI (Chapters 5.4 and 6.4).

5.2 SPI Bus Pin Descriptions

SDI Pin

DCLK

SDATA

SCI Pin

XCS

SCK

Description

Active low chip select input. A high level forces the serial interface into

standby mode, ending the current operation. A high level also forces serial

output (SO) to high impedance state. There is no chip select for SDI, which

is always active.

Serial clock input. The serial clock is also used internally as the master

clock for the register interface.

SCK can be gated or continuous. In either case, the ï¬rst rising clock edge

after XCS has gone low marks the ï¬rst bit to be written (clock 0 in the

following ï¬gures).

Serial input. SI is sampled on the rising SCK edge, if XCS is low.

Serial output. In reads, data is shifted out on the falling SCK edge.

In writes SO is at a high impedance state.

5.3 Serial Protocol for Serial Data Interface (SDI)

The serial data interface can operate in either master or slave mode. In master mode, VS1001k generates

the DCLK signal, which can be selected to be either 512 or 1024 kHz. In slave mode, the DCLK signal

is generated by an external circuit.

The data (SDATA signal) can be clocked in at either the rising or falling edge of the DCLK. (Chapter 6.5).

The VS1001k chip assumes its input to be byte-sychronized. I.e. the internal operation of the decoder

does not search for byte synchronization of the frames from the data stream, but instead assumes the

data to be correctly byte-aligned. The bytes can be transmitted either MSB or LSB ï¬rst, depending of

contents of SCI register MODE (Chapter 6.5).

BSYNC

SDATA

DCLK

Figure 7: BSYNC Signal.

To ensure correct byte-alignment of the input bitstream, the serial data interface has a BSYNC signal.

Version 4.14, 2004-02-10

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