VS1001K Datasheet, PDF (20/40 Pages) List of Unclassifed Manufacturers – MPEG AUDIO CODEC

VLSI
Solution ^y
DATASHEET
VS1001K
5. SPI BUSES
5.5 SPI Timing Diagram
XCS
SCK
tXCSS
0
1
tWL tWH
14
15
16
tXCSH
tXCS
SI
tSU
tH
SO
tZ
tV
tDIS
Figure 10: SPI Timing Diagram.
Symbol Min Max Unit
tXCSS
5
ns
tSU
10
ns
tH
42
ns
tZ
42 ns
tWL
100
ns
tWH
100
ns
tV
42 ns
tXCSH 10
ns
tXCS
2
XTALI cycles
tDIS
1 XTALI cycles
Note: As tXCS must be at least 2 clock cycles, the maximum speed for the SPI bus is 1/4 of VS1001k’s
internal clock speed. For details, see Application Notes for VS10XX.
Version 4.14, 2004-02-10
20