VS1001K Datasheet, PDF (25/40 Pages) List of Unclassifed Manufacturers – MPEG AUDIO CODEC

VLSI
Solution ^y
DATASHEET
VS1001K
6. FUNCTIONAL DESCRIPTION
6.5.2 STATUS (RW)
STATUS contains information on the current status of the VS1001k. Bits 1 and 0 are used to control
analog output volume: 0 = -0 dB, 1 = -6 dB, 3 = -12 dB. Bit 2 is analog powerdown bit. When set to 1,
analog is put to powerdown.
Note: writing to register VOL will automatically set the analog output volume, and muting if necessary.
Thus, the user needn’t worry about this register.
6.5.3 INT FCNTLH (-)
INT FCTLH is not a user-accessible register.
6.5.4 CLOCKF (RW)
CLOCKF is used to tell if the input clock XTALI is running at something else than 24.576 MHz. XTALI
is set in 2 kHz steps. Thus, the formula for calculating the correct value for this register is XT ALI/2000
(XTALI is in Hz). Values may be between 0..32767, although hardware limits the highest allowed speed.
Also, with lower-than 24.576 MHz speeds all sample rates and bit-stream widths are no longer available.
Setting the MSB of CLOCKF to 1 activates internal clock-doubling. A clock of upto 15 MHz may be
doubled depending on the voltage provided to the chip.
Note: CLOCKF must be set before beginning decoding MP3 data; otherwise the sample rate will not be
set correctly.
Example 1: For a 26 MHz clock the value would be 26000000/2000 = 13000.
Example 2: For a 13 MHz external clock and using internal clock-doubling for a 26 MHz internal
frequency, the value would be 0x8000 + (13000000/2000) = 39268.
Example 3: For a 24.576 MHz clock the value would be either 24576000/2000 = 12288, or just the
default value 0. For this clock frequency, CLOCKF doesn’t need to be set at all.
6.5.5 DECODE TIME (R)
When decoding correct data, current decoded time is shown in this register in full seconds.
Version 4.14, 2004-02-10
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