VS1001K Datasheet, PDF (24/40 Pages) List of Unclassifed Manufacturers – MPEG AUDIO CODEC

VLSI
Solution ^y
DATASHEET
VS1001K
6. FUNCTIONAL DESCRIPTION
power is needed when activating this feature, see Application Notes for VS10XX.
ampl/dB
+3
+2
+1
0
−1
−2
−3
f/Hz
10
20
50
100 200 500 1k
2k
5k
10k 20k
Figure 12: Built-In Bass/Treble Enhancer Frequency Response at 44.1 kHz.
SM DACT defines the active edge of data clock for SDI.
SM BITORD defines the data bit order inside a byte for SDI. When clear the most significant bit of a
byte is sent first and when set, the least significant bit is sent first. Bytes are, however, still sent in the
default order. This register bit has no effect on the SCI bus.
SM IBMODE sets input bus to master mode. Master mode has not been tested, and its use is not recom-
mended.
SM IBCLK sets the bus clock speed when VS1001k is the master.
Version 4.14, 2004-02-10
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