M12L128324A_1 Datasheet, PDF (45/49 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 32 Bit x 4 Banks Synchronous DRAM

ESMT
Self Refresh Entry & Exit Cycle
M12L128324A
Operation temperature condition -40°C~85°C
0
CLOCK
CKE
CS
1
2
3
*Note2
*Note1
tSS
4
5
6
7
*Note3
8
9
10 11 12 13 14 15 16 17 18 19
*Note4
tRCmin
*Note6
*Note5
RAS
CAS
ADDR
*Note7
BA0,BA1
A10/AP
DQ
Hi-Z
Hi-Z
WE
DQM
Self Refresh Entry
Self Ref resh Exit
Auto Refresh
: Don't care
*Note : TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1
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